Patents by Inventor Eliel Louzoun
Eliel Louzoun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960439Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.Type: GrantFiled: March 9, 2022Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Janusz Jurski, Myron Loewen, Mariusz Oriol, Patrick Schoeller, Jerry Backer, Richard Marian Thomaiyar, Eliel Louzoun, Piotr Matuszczak
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Publication number: 20240028381Abstract: A network interface device executes an input/output (I/O) virtualization manager to identify a virtual device defined to include resources of a particular virtual functions in a plurality of virtual functions associated with a physical function of a device. An operation is identified to be performed between the virtual device and a system image hosted by a host system coupled to the network interface device. The network interface device emulates the virtual device in the operation using the I/O virtualization manager.Type: ApplicationFiled: September 28, 2023Publication date: January 25, 2024Applicant: Intel CorporationInventors: Shaopeng He, Yadong Li, Anjali Singhai Jain, Eliel Louzoun, Israel Ben-Shahar, Brad A. Burres, Bartosz Pawlowski, Anton Nadezhdin, Rashmi Hanagal Nagabhushana, Rupin H. Vakharwala
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Patent number: 11805081Abstract: Packets received non-contiguously from a network are processed by a network interface controller by coalescing received packet payload into receive buffers on a receive buffer queue and writing descriptors associated with the receive buffers for a same flow consecutively in a receive completion queue. System performance is optimized by reusing a small working set of provisioned receive buffers to minimize the memory footprint of memory allocated to store packet data. The remainder of the provisioned buffers are in an overflow queue and can be assigned to the network interface controller if the small working set of receive buffers is not sufficient to keep up with the received packet rate. The receive buffer queue can be refilled based on either timers or when the number of buffers in the receive buffer queue is below a configurable low watermark.Type: GrantFiled: March 2, 2020Date of Patent: October 31, 2023Assignee: Intel CorporationInventors: Linden Cornett, Noam Elati, Anjali Singhai Jain, Parthasarathy Sarangam, Eliel Louzoun, Manasi Deval
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Publication number: 20230153143Abstract: Creating hybrid virtual devices using a plurality of physical functions. A processor of a device may identify a plurality of physical functions accessible to the device, the plurality of physical functions including a first physical function and a second physical function. The processor may create a virtual device to comprise the first physical function to provide a first capability and the second physical function to provide a second capability, wherein the first capability and second capability are different capabilities.Type: ApplicationFiled: January 17, 2023Publication date: May 18, 2023Applicant: Intel CorporationInventors: SHAOPENG HE, ANJALI SINGHAI JAIN, UTKARSH Y. KAKAIYA, YADONG LI, ELIEL LOUZOUN, KUN TIAN, BRADLEY BURRES, RORY HARRIS, YAN ZHAO
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Publication number: 20230108461Abstract: Examples described herein relate to circuitry configured to generate at least one virtual device interface to utilize the processor circuitry and provide the at least one virtual device interface to a server to assign to a process to provide the process with capability to utilize the processor circuitry. In some examples, the processor circuitry is to perform one or more of local area network access, cryptographic processing, and/or storage access. In some examples, the storage access comprises access to one or more Non-volatile Memory Express (NVMe) devices.Type: ApplicationFiled: November 30, 2022Publication date: April 6, 2023Inventors: Shaopeng HE, Anjali Singhai JAIN, Yadong LI, Eliel LOUZOUN, Bradley A. BURRES, Utkarsh Y. KAKAIYA, Kun TIAN, Baolu LU, Yan ZHAO, Madhusudan CHITTIM MUNIRATHNAM, Lingyu LIU
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Patent number: 11575620Abstract: Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.Type: GrantFiled: March 27, 2020Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Eliel Louzoun, Anjali Singhai Jain, Ben-Zion Friedman
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Patent number: 11531752Abstract: Technologies for control plane separation at a network interface controller (NIC) of a compute device configured to transmit, by a resource of the compute device, commands to a physical function managed by a network interface controller (NIC) of the compute device. The NIC is further to establish a data plane separate from a control plane, wherein the control plane comprises one of the trusted control path and the untrusted control path. Additionally, the resource is configured to transmit the commands via one of the trusted control path or the untrusted control path based on a trust level associated with the physical function. Other embodiments are described herein.Type: GrantFiled: September 26, 2018Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Akeem Abodunrin, Lev Faerman, Scott Dubal, Suyog Kulkarni, Anjali Singhai Jain, Eliel Louzoun, Nrupal Jani, Yadong Li, Eliezer Tamir, Arvind Srinivasan, Ben-Zion Friedman
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Publication number: 20220261178Abstract: Examples described herein relate to a packet processing device that includes circuitry to receive an address translation for a virtual to physical address prior to receipt of a GPUDirect remote direct memory access (RDMA) operation, wherein the address translation is provided at initiation of a process executed by a host system and circuitry to apply the address translation for a received GPUDirect RDMA operation.Type: ApplicationFiled: March 7, 2022Publication date: August 18, 2022Inventors: Shaopeng HE, Yadong LI, Anjali Singhai JAIN, Kun TIAN, Yan ZHAO, Yaozu DONG, Baolu LU, Rajesh M. SANKARAN, Eliel LOUZOUN, Rupin H. VAKHARWALA, David HARRIMAN, Saurabh GAYEN, Philip LANTZ, Israel BEN SHAHAR, Kenneth G. KEELS
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Publication number: 20220197859Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices.Type: ApplicationFiled: March 9, 2022Publication date: June 23, 2022Inventors: Janusz JURSKI, Myron LOEWEN, Mariusz ORIOL, Patrick SCHOELLER, Jerry BACKER, Richard Marian THOMAIYAR, Eliel LOUZOUN, Piotr MATUSZCZAK
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Publication number: 20220141133Abstract: An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments.Type: ApplicationFiled: January 18, 2022Publication date: May 5, 2022Inventors: Eliel LOUZOUN, Manasi DEVAL, Stephen DOYLE, Noam ELATI, Patrick FLEMING, Gregory BOWERS
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Publication number: 20220086226Abstract: Examples described herein relate to a network interface device comprising: a device interface; at least one processor; a direct memory access (DMA) device; and a packet processing circuitry. In some examples, the at least one processor, when operational, is configured to: in connection with a first operation: perform a format translation of a first descriptor from a first format associated with an emulated device to a second format associated with the packet processing circuitry and provide, to the packet processing circuitry, the translated first descriptor. In some examples, the at least one processor, when operational, is configured to: in connection with a second operation: perform a descriptor format translation of a second descriptor from the second format associated with the packet processing circuitry to the first format associated with the emulated software device and provide, to the emulated device, the translated second descriptor.Type: ApplicationFiled: September 23, 2021Publication date: March 17, 2022Inventors: Anjali Singhai JAIN, Noam ELATI, Eliel LOUZOUN, Daniel DALY
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Patent number: 11271856Abstract: An apparatus, a method and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments.Type: GrantFiled: May 17, 2019Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Eliel Louzoun, Manasi Deval, Stephen Doyle, Noam Elati, Patrick Fleming, Gregory Bowers
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Publication number: 20220045950Abstract: Disclosed is a mechanism for maintaining a single lookup table entry for symmetric/bidirectional flows. Multiple recipes are stored for each flow. A recipe is employed to select address information from an incoming packet header based on the packet's direction. The address information and an index are employed to generate a lookup key to find the single lookup table entry with the pertinent switching information. The recipe further indicates action pointers in the lookup table entry that are specific to direction. The action pointers point to an address in an action table that contains instructions for actions that are applied to the packet during switching based on the packet's direction.Type: ApplicationFiled: October 25, 2021Publication date: February 10, 2022Inventors: Eliel Louzoun, Ben-Zion Friedman, Eli SORIN, Nir Haber
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Patent number: 11194735Abstract: Technologies for I/O device virtualization include a computing device with an I/O device that includes a physical function, multiple virtual functions, and multiple assignable resources, such as I/O queues. The physical function assigns an assignable resource to a virtual function. The computing device configures a page table mapping from a virtual function memory page located in a configuration space of the virtual function to a physical function memory page located in a configuration space of the physical function. The virtual function memory page includes a control register for the assignable resource, and the physical function memory page includes another control register for the assignable resource. A value may be written to the control register in the virtual function memory page. A processor of the computing device translates the virtual function memory page to the physical function memory page using the page mapping. Other embodiments are described and claimed.Type: GrantFiled: September 29, 2017Date of Patent: December 7, 2021Assignee: Intel CorporationInventors: Ben-Zion Friedman, Eliel Louzoun
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Patent number: 11159427Abstract: Disclosed is a mechanism for maintaining a single lookup table entry for symmetric/bidirectional flows. Multiple recipes are stored for each flow. A recipe is employed to select address information from an incoming packet header based on the packet's direction. The address information and an index are employed to generate a lookup key to find the single lookup table entry with the pertinent switching information. The recipe further indicates action pointers in the lookup table entry that are specific to direction. The action pointers point to an address in an action table that contains instructions for actions that are applied to the packet during switching based on the packet's direction.Type: GrantFiled: March 31, 2017Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Eliel Louzoun, Ben-Zion Friedman, Eli Sorin, Nir Haber
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Patent number: 11099872Abstract: Techniques are described that can be used to enable a transfer of an operating system from one machine to another. The transfer permits the operating system to be available to the target machine at buffers that are accessible to one or more application or other logic. In some implementations, information related to an operating system migration is stored in a buffer that is accessible to an application that is to use the information and thereby avoids a copy of such information from an intermediate buffer to an application buffer.Type: GrantFiled: November 5, 2018Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Eliel Louzoun, Mickey Gutman, Gregory Cummins
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Publication number: 20210006511Abstract: Methods and apparatus for software-controlled active-backup mode of link aggregation for RDMA and virtual functions. A Network Interface Controller (NIC) includes hardware implementing first and second physical functions (PFs) including transmit and receive resources to support data transfers via first and second ports. A bonding group is created with the first and second PFs. The first PF as an active PF and used for primary data transfers while implementing the second PF as a backup PF. On a link or port failure of the active PF, the bonding group is reconfigured to employ transmit and receive resources of the backup PF such that those resources are shared with the active PF. Data transfers are then performed using the shared resources of the active PF and the backup PF. Embodiments may support RDMA data transfers using PF bonding and the solution may be implemented in virtualized environments including virtual machines (VMs) in a manner transparent to the VMs.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Inventors: Piotr Uminski, Anjali Singhai Jain, Eliel Louzoun, Robert O. Sharp, Vivek Kashyap
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Publication number: 20200228467Abstract: Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.Type: ApplicationFiled: March 27, 2020Publication date: July 16, 2020Inventors: Eliel LOUZOUN, Anjali Singhai JAIN, Ben-Zion FRIEDMAN
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Publication number: 20200210359Abstract: Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.Type: ApplicationFiled: March 10, 2020Publication date: July 2, 2020Inventors: Linden CORNETT, Eliel LOUZOUN, Anjali Singhai JAIN, Ronen Aharon HYATT, Danny VOLKIND, Noam ELATI, Nadav TURBOVICH
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Publication number: 20200204503Abstract: Packets received non-contiguously from a network are processed by a network interface controller by coalescing received packet payload into receive buffers on a receive buffer queue and writing descriptors associated with the receive buffers for a same flow consecutively in a receive completion queue. System performance is optimized by reusing a small working set of provisioned receive buffers to minimize the memory footprint of memory allocated to store packet data. The remainder of the provisioned buffers are in an overflow queue and can be assigned to the network interface controller if the small working set of receive buffers is not sufficient to keep up with the received packet rate. The receive buffer queue can be refilled based on either timers or when the number of buffers in the receive buffer queue is below a configurable low watermark.Type: ApplicationFiled: March 2, 2020Publication date: June 25, 2020Inventors: Linden CORNETT, Noam ELATI, Anjali Singhai JAIN, Parthasarathy SARANGAM, Eliel LOUZOUN, Manasi DEVAL