Abstract: Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.

Abstract: There is disclosed in an example, a computer-implemented method of providing network function virtualization orchestration (NFVO), including: determining that a first virtual network function (VNF) instance, providing a virtual service appliance on a virtual network, is to be migrated; provisioning a second VNF instance of the virtual service appliance; cloning configuration data from the first VNF to the second VNF; starting the second VNF without copying traffic data; and halting the first VNF. There is also disclosed an apparatus for performing the method, and a computer-readable medium having instructions for performing the method.

Abstract: An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing device may include: a processor system including at least one first processing core having a first instruction set architecture (ISA), and at least one second processing core having a second ISA different from the first ISA; and a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA and a second binary representation of the program for the second ISA, and the memory device has stored thereon data for the program having an in-memory representation compatible with both the first ISA and the second ISA.

Abstract: Examples are disclosed for replicating data between storage servers. In some examples, a network input/output (I/O) device coupled to either a client device or to a storage server may exchange remote direct memory access (RDMA) commands or RDMA completion commands associated with replicating data received from the client device. The data may be replicated to a plurality of storage servers interconnect to each other and/or the client device via respective network communication links. Other examples are described and claimed.

Abstract: Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device. Data having a destination associated with the first processing element may be received by the input/output device. The exchanged key may be used to encrypt the received data. The encrypted data may then be sent to a buffer maintained at least in part in a memory for the network device. The memory may be arranged to enable sharing of the buffer with at least a second processing element operating on the network device. Examples are also disclosed for the processing element to receive an indication of the storing of the encrypted data in the buffer. The processing element may then obtain the encrypted data from the buffer and decrypt the data using the exchanged key.

Abstract: Technologies for providing FPGA infrastructure-as-a-service include a computing device having an FPGA, scheduler logic, and design loader logic. The scheduler logic selects an FPGA application for execution and the design loader logic loads a design image into the FPGA. The scheduler logic receives a ready signal from the FGPA in response to loading the design and sends a start signal to the FPGA application. The FPGA executes the FPGA application in response to sending the start signal. The scheduler logic may time-share the FPGA among multiple FPGA applications. The computing device may include signaling logic to manage signals between a user process and the FPGA application and DMA logic to manage bulk data transfer between the user process and the FPGA application. The computing device may include a user process linked to an FGPA library executed by a processor of the computing device. Other embodiments are described and claimed.

Abstract: Embodiments may be generally directed to techniques to receive rate meter information indicating an occurrence of a rate meter event, the rate meter event determined by a rate meter associated with a network element in a software defined network (SDN) environment. determine a requirement for a service provided by the network element is not met based on the rate meter event detected by the rate meter. Embodiments may also include techniques to determine a corrective action based on the requirement not met, the corrective action to cause the requirement to be met for the service provided by the network element in the SDN environment and cause the correct action to be performed for the network element.

Abstract: A collection of techniques allow for the detection of covert malware that attempts to hide its existence on a system by leveraging both trusted hardware event counters and the particular memory addresses (as well as the sequences of such addresses) of the instructions that are generating the suspected malicious activity. By monitoring the address distribution's specific patterns over time, one can build a behavioral model (i.e., “fingerprint”) of a particular process—and later attempt to match suspected malicious processes to the stored behavioral models. Whenever the actual measured behavior of a suspected malicious process fails to match said stored behavioral models, the system or system administrator may attempt to perform rehabilitative actions on the computer system to locate and remove the malware hiding on the system.

Abstract: Examples are disclosed for forwarding or receiving data segments associated with a large data packets. In some examples, a large data packet may be segmented into a number of data segments having separate headers that include identifiers to associate the data segments with the large data packet. The data segments with separate headers may then be forwarded from a network node via a communication channel. In other examples, the data segments with separate headers may be received at another network node and then recombined to form the large data packet at the other network node. Other examples are described and claimed.

Abstract: The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances.

Abstract: Examples are disclosed for use of vendor defined messages to execute a command to access a storage device maintained at a server. In some examples, a network input/output device coupled to the server may receive the command from a client remote to the server for the client to access the storage device. For these examples, elements or components of the network input/output device may be capable of forwarding the command either directly to a Non-Volatile Memory Express (NVMe) controller that controls the storage device or to a manageability module coupled between the network input/out device and the NVMe controller. Vendor specific information may be forwarded with the command and used by either the NVMe controller or the manageability module to facilitate execution of the command. Other examples are described and claimed.

Abstract: An embodiment may include circuitry that may be capable of performing operations that may include generating, at least in part, at least one message to announce that at least one network node (1) is requesting, at least in part, that one or more transmissions to the at least one network node be postponed, at least in part, and/or (2) is entering, at least in part after issuance of the at least one message, a relatively lower power state relative to a relatively higher power state. Additionally or alternatively, the operations may include, in response, at least in part, to the at least one message, postponing, at least in part, at least one intermediate node at least one transmission (received by the at least one intermediate node) to the at least one network node. Many alternatives, variations, and/or modifications are possible without departing from this embodiment.

Abstract: Generally, this disclosure provides systems, methods and computer readable media for management of sockets and device queues for reduced latency packet processing. The method may include maintaining a unique-list comprising entries identifying device queues and an associated unique socket for each of the device queues, the unique socket selected from a plurality of sockets configured to receive packets; busy-polling the device queues on the unique-list; receiving a packet from one of the plurality of sockets; and updating the unique-list in response to detecting that the received packet was provided by an interrupt processing module. The updating may include identifying a device queue associated with the received packet; identifying a socket associated with the received packet; and if the identified device queue is not on one of the entries on the unique-list, creating a new entry on the unique-list, the new entry comprising the identified device queue and the identified socket.

Abstract: Various embodiments are generally directed to techniques for cooperation between a higher function core and a lower power core to minimize the effects of interrupts on a current flow of execution of instructions. An apparatus may include a lower power core comprising a first instruction pipeline, the lower power core to stop a first flow of execution in the first instruction pipeline and execute instructions of a handler routine in the first instruction pipeline to perform a first task of handling an interrupt; and a higher function core comprising a second instruction pipeline, the higher function core to, following the performance of the first task, schedule execution of instructions of a second task of handling the interrupt in the second instruction pipeline to follow a second flow of execution in the second instruction pipeline, the first task more time-sensitive than the second task. Other embodiments are described and claimed.

Abstract: The present disclosure is directed to a unified device interface for a multi-bus system. In at least one embodiment, a system may comprise more than one data bus. Each data bus may be to convey data between an operating system (OS) and at least one device in the system, wherein a plurality of driver instances may facilitate interaction between the OS and a device via one or more of the data buses. In one embodiment, a main driver instance may be determined from the plurality of driver instances to present the device to the OS and coordinate operation of other driver instances. The other driver instances may map addresses in the memory of processing entities corresponding to each of the data buses and report these mappings to the main driver instance. Alternatively, a supervisory driver may be loaded to present the device and to control operation of the driver instances.

Abstract: Scalable techniques for data transfer between virtual machines (VMs) are described. In an example embodiment, an apparatus may comprise circuitry, a virtual machine management component for execution by the circuitry to define a plurality of public virtual memory spaces and assign each one of the plurality of public virtual memory spaces to a respective one of a plurality of VMs including a first VM and a second VM, and a virtual machine execution component for execution by the circuitry to execute a first virtual machine process corresponding to the first VM and a second virtual machine process corresponding to the second VM, the first virtual machine process to identify data to be provided to the second VM by the first VM and provide the data to the second VM by writing to a public virtual memory space assigned to the first VM. Other embodiments are described and claimed.