Patents by Inventor Eliot K. Broadbent

Eliot K. Broadbent has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5230741
    Abstract: A suitable inert gas such as argon or a mixture of inert and reactive gases such as argon and hydrogen is introduced onto the backside of wafers being processed in a CVD reactor during the deposition of tungsten or other metals, metal nitrides and silicides, to avoid deposition of material on the backside of the wafers being processed. Each process station includes a gas dispersion head disposed over a platen. A vacuum chuck including a number of radial and circular vacuum grooves in the top surface of the platen is provided for holding the wafer in place. A platen heater is provided under the platen. Backside gas is heated in and about the bottom of the platen, and introduced through a circular groove in the peripheral region outside of the outermost vacuum groove of the vacuum chuck. Backside gas pressure is maintained in this peripheral region at a level greater than the CVD chamber pressure.
    Type: Grant
    Filed: July 16, 1990
    Date of Patent: July 27, 1993
    Assignee: Novellus Systems, Inc.
    Inventors: Everhardus P. van de Ven, Eliot K. Broadbent, Jeffrey C. Benzing, Barry L. Chin, Christopher W. Burkhart
  • Patent number: 5188717
    Abstract: A magnetism sputtering apparatus is provided with a movable magnetic track which is a closed curve essentially in the shape of a kidney bean, the closed curve being generated in part by a spiral curve. The magnet track is positioned behind the target of the sputtering apparatus, and it is simultaneously rotated about a center of rotation and caused to oscillate substantially radially with respect to said center of rotation. The combined rotational and oscillatory motion provides a substantially uniform magnetic flux over a major annular portion of the target while ensuring that some degree of sputtering occurs in all regions of the target, including regions near the center and periphery of the target. This arrangement has been found suitable for providing a highly uniform deposition of target material on large diameter substrates.
    Type: Grant
    Filed: September 12, 1991
    Date of Patent: February 23, 1993
    Assignee: Novellus Systems, Inc.
    Inventors: Eliot K. Broadbent, Kenneth C. Miller
  • Patent number: 5171415
    Abstract: The movable magnet track housing of a magnetron sputtering apparatus is provided with a cooling channel and a plurality of nozzles for cooling the backing plate of the magnetron sputtering target. A cooling liquid is delivered to the cooling channel, which distributes the pressure of the liquid to its nozzles. Fluid dispensed from the nozzles is directed at a given area on the back of the target backing plate to make cooling more efficient. The flattened teardrop shape of the magnet track is suitable for achieving uniform magnetic flux in an annular region when rotated about a predetermined center of rotation. The magnet track is rotated circularly and moved radially during magnetron sputtering to achieve substantially uniform magnetic flux over a major annular region of the target, while suitably eroding the center and perimeter regions of the target.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: December 15, 1992
    Assignee: Novellus Systems, Inc.
    Inventors: Kenneth C. Miller, Eliot K. Broadbent
  • Patent number: 5133284
    Abstract: A suitable inert thermal gas such as argon is introduced onto the backside of wafers being processed in a CVD reactor during the deposition of tungsten or other metals and silicides, to avoid deposition of material on the backside of the wafers being processed. Each process station includes a gas dispersion head disposed over a platen. The platen has a circular depresssion for receiving a wafer, and an annular groove provided in the floor of the depression, near the wall thereof. Heated and pressurized backside gas is introduced into the groove so that the wafer is maintained in a position above the floor of the depression but still within it. In this manner, backside gas vents from beneath the edge of the wafer on the platen and prevents the process gases from contacting the wafer in a transfer region above the platen, so that the wafer can be transported to or from the platen with a suitable wafer transfer mechanism.
    Type: Grant
    Filed: July 16, 1990
    Date of Patent: July 28, 1992
    Assignees: National Semiconductor Corp., Novellus Systems
    Inventors: Michael E. Thomas, Everhardus P. van de Van, Eliot K. Broadbent
  • Patent number: 5063175
    Abstract: A planar electrical interconnection system suitable for an integrated circuit is created by a process in which an insulating layer (31) having a planar upper surface is formed on a substructure after which openings (32) are etched through the insulating layer. A conductive planarizing layer (33) having a planar upper surface is formed on the insulating layer and in the openings by an operation involving isotropic deposition of a material, preferably tungsten, to create at least a portion of the planarizing layer extending from its upper surface partway into the openings. The planarizing layer is then etched down to the insulating layer. Consequently, its upper surface is coplanar with that of the material (33') in the openings. The foregoing steps are repeated to create another coplanar conductive/insulating layer (34 and 36'). If the lower openings are vias while the upper openings are grooves, the result is a planar interconnect level. Further planar interconnect levels can be formed in the same way.
    Type: Grant
    Filed: December 16, 1988
    Date of Patent: November 5, 1991
    Assignee: North American Philips Corp., Signetics Division
    Inventor: Eliot K. Broadbent
  • Patent number: 4976809
    Abstract: Aluminum alloy polycrystalline conductors having reduced electro-migration tendencies are formed in a semiconductor device by applying a thin film of aluminum or aluminum alloy to an array of shallow holes provided in a dielectric layer the array being patterned according to a desired interconnection pattern. A thin film of aluminum or aluminum alloy is then scanned with a laser beam sufficient to melt the film and cause it to planarize. An oriented crystal structure is formed with grain boundaries being aligned orthogonally to the rows and column of the hole pattern. A photoresist mask is then aligned with the resultant crystal structure in a manner such that boundaries extend substantially only in a direction across the width of the desired conductor lines. The aluminum which is present in the crystal structure outside the desired conductor line is then removed by plasma etching through the mask.
    Type: Grant
    Filed: December 18, 1989
    Date of Patent: December 11, 1990
    Assignee: North American Philips Corp, Signetics Division
    Inventor: Eliot K. Broadbent
  • Patent number: 4612257
    Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.
    Type: Grant
    Filed: October 9, 1984
    Date of Patent: September 16, 1986
    Assignee: Signetics Corporation
    Inventor: Eliot K. Broadbent
  • Patent number: 4517225
    Abstract: A structure for an electrical interconnection suitable for a semiconductor integrated circuit is made by a process utilizing selective tungsten deposition at low pressure to form an intermediate conductive layer without significantly ablating nearby insulating material.
    Type: Grant
    Filed: May 2, 1983
    Date of Patent: May 14, 1985
    Assignee: Signetics Corporation
    Inventor: Eliot K. Broadbent
  • Patent number: 4495221
    Abstract: A layer of a conductive material consisting of aluminum alone or in combination with a small percentage of copper and/or silicon is formed on a semiconductor surface in a two-step deposition process in such a manner as to largely avoid serious continuity defects in the layer.
    Type: Grant
    Filed: October 26, 1982
    Date of Patent: January 22, 1985
    Assignee: Signetics Corporation
    Inventor: Eliot K. Broadbent