Abstract: A digital communication system for transmitting and receiving video data signals and control data signals over a transmission line comprises an open-loop equalizer circuit and a control data extension circuit. The open-loop equalizer circuit is operable to receive video signals transmitted over the transmission line and output equalized video data signals. The control data extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the control data signal, and clamp the receive end of the transmission line during a negative transition of the control data signal.

Abstract: Systems and methods for tuning a phase locked loop (PLL) having a segmented voltage controlled oscillator (VCO) to an input frequency are provided. The PLL is reset and its VCO is coarse tuned until the input frequency is within a first predetermined threshold of the VCO center frequency. The input frequency is then compared to a clock reference signal to determine whether the input frequency has stabilized. After the input frequency has stabilized, the input frequency is continuously monitored by comparing it to the clock reference signal to determine whether the input frequency is varying, and if the input frequency is varying by more than a second predetermined threshold, then the PLL is reset.

Abstract: Systems and method for controlling the gain of an equalizer are provided. In these systems and methods, bit errors in a serial data stream received by an equalizer are detected, and the gain of the equalizer is set in response to the detected bit errors in the serial data stream.