Patents by Inventor Elizabeth A. Chambers

Elizabeth A. Chambers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10144470
    Abstract: A vehicle seat includes a cushion material and a cover for covering the cushion material. The cover includes a load receiving portion configured to receive a load of a seated occupant. The load receiving portion includes a large thickness portion and a small thickness portion that are located next to each other in a first direction that intersects with a thickness direction of the cover. Each of the large and small thickness portions includes an elastic layer compressive in the thickness direction and a lower cover layer located closer to the cushion material than the elastic layer in the thickness direction. The elastic layer of the small thickness portion is compressed such that the thickness of the small thickness portion is smaller than the thickness of the large thickness portion. The lower cover layer of the large thickness portion is partially cut off to form a cutoff portion.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 4, 2018
    Assignees: TS Tech Co., Ltd., Harley-Davidson Motor Company Group, LLC
    Inventors: Hideki Tokumoto, Sam Schacht, Elizabeth Chambers, Justin Schrand, Katsuhiro Kiya, Anthony Senger, Kenneth Luckjohn, Ben McGinley
  • Publication number: 20180297659
    Abstract: A vehicle seat includes a cushion material and a cover for covering the cushion material. The cover includes a load receiving portion configured to receive a load of a seated occupant. The load receiving portion includes a large thickness portion and a small thickness portion that are located next to each other in a first direction that intersects with a thickness direction of the cover. Each of the large and small thickness portions includes an elastic layer compressive in the thickness direction and a lower cover layer located closer to the cushion material than the elastic layer in the thickness direction. The elastic layer of the small thickness portion is compressed such that the thickness of the small thickness portion is smaller than the thickness of the large thickness portion. The lower cover layer of the large thickness portion is partially cut off to form a cutoff portion.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 18, 2018
    Inventors: Hideki Tokumoto, Sam Schacht, Elizabeth Chambers, Justin Schrand, Katsuhiro Kiya, Anthony Senger, Kenneth Luckjohn, Ben McGinley
  • Patent number: 5943591
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: August 24, 1999
    Assignee: VLSI Technology
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5795815
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: August 18, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5686171
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: November 11, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5048678
    Abstract: This invention relates to a direct dispensing and self-contained surgical suture package. The package can comprise a first part having a strippable envelope, and a second part self-contained therein.
    Type: Grant
    Filed: April 19, 1989
    Date of Patent: September 17, 1991
    Assignee: American Cyanamid Company
    Inventor: Elizabeth A. Chambers
  • Patent number: D382960
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: August 26, 1997
    Assignee: American Cyanamid Company
    Inventor: Elizabeth A. Chambers
  • Patent number: D401339
    Type: Grant
    Filed: February 4, 1997
    Date of Patent: November 17, 1998
    Assignee: Tyco Group S.A.R.L.
    Inventor: Elizabeth A. Chambers
  • Patent number: D401692
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: November 24, 1998
    Assignee: Tyco Group S.A.R.L.
    Inventor: Elizabeth A. Chambers