Patents by Inventor Elizabeth Lair Gerhard
Elizabeth Lair Gerhard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8331180Abstract: A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved.Type: GrantFiled: September 30, 2010Date of Patent: December 11, 2012Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
-
Patent number: 8213249Abstract: A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value.Type: GrantFiled: May 27, 2010Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
-
Publication number: 20120081949Abstract: A static random access memory (SRAM) includes an SRAM cell to store a bit of data. A word line accesses the SRAM cell, which, responsively, during a read, drives either a bit line true (BLT) or a bit line complement (BLC) low. Both BLT and BLC are precharged to a supply voltage, then, subsequently are discharged to a reference voltage, lower than the supply voltage, prior to the word line being activated. Because the bit lines are at a voltage lower than the supply voltage when the SRAM cell is activated, the SRAM cell stability is improved.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
-
Publication number: 20110292748Abstract: A method and static random access memory (SRAM) circuit for implementing low power data predicting local evaluation for double pumped arrays, and a design structure on which the subject circuit reside are provided. A novel variation of a domino read local evaluation circuit accurately predicts the write data for the next cycle. The domino read local evaluation circuit uses static write data set up prior to a write enable signal to determine the value of the data that is being written into the array. When the data being written to the array matches the data last read the local bitlines stay in their previous state. When the data being written is opposite of the data last read then the bit lines are precharged to the precharge value.Type: ApplicationFiled: May 27, 2010Publication date: December 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Allen Adams, Sharon Huertas Cesky, Elizabeth Lair Gerhard, Jeffrey Milton Scherer
-
Patent number: 7783943Abstract: A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.Type: GrantFiled: May 15, 2008Date of Patent: August 24, 2010Assignee: International Business Machines CorporationInventors: Chad Allen Adams, Elizabeth Lair Gerhard, Sharon Huertas Cesky, Jeffrey Milton Scherer
-
Patent number: 7715221Abstract: A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.Type: GrantFiled: June 23, 2008Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, Elizabeth Lair Gerhard, Omer Heymann, Amira Rozenfeld
-
Publication number: 20090285039Abstract: A method and apparatus for write assist for a static random access memory (SRAM) array, is provided, which increases the write ability of the SRAM cell by locally raising the source voltage. One embodiment involves locally generating a virtual ground for write assist on column selected SRAM cells, including locally raising the source voltage to increase the write ability of the SRAM cell; wherein locally raising the source voltage comprises locally generating a virtual source/ground node for boosting the write ability of a column of SRAM cells without using an additional on-chip or off-chip supply; thereby decreasing the voltage differential across the source and supply of the column of SRAM cells during a write, and restoring the standard chip differential during a read.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Chad Allen Adams, Elizabeth Lair Gerhard, Sharon Huertas Cesky, Jeffrey Milton Scherer
-
Publication number: 20090287971Abstract: A method and apparatus for testing a random access memory device is provided. One embodiment involves providing an interface between Logic Built in Self Test (LBIST) and Array Built in Self Test (ABIST) paths for memory testing, including providing a cross-coupled NAND device with an LBIST test path; configuring the cross-coupled NAND device for interfacing ABIST and LBIST paths by modeling a worst case scenario for timing from a domino read static random access memory (SRAM) array; and modifying data in the cross-coupled NAND device using an LBIST controlled data path at essentially the latest point in time when a read may propagate from the array to provide full AC test coverage of down stream logic.Type: ApplicationFiled: May 15, 2008Publication date: November 19, 2009Applicant: International Business Machines CorporationInventors: Chad Allen Adams, Elizabeth Lair Gerhard, Sharon Huertas Cesky, Jeffrey Milton Scherer
-
Publication number: 20080273402Abstract: A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.Type: ApplicationFiled: June 23, 2008Publication date: November 6, 2008Applicant: International Business Machines CorporationInventors: Todd Alan Christensen, Elizabeth Lair Gerhard, Omer Heymann, Amira Rozenfeld
-
Patent number: 7414878Abstract: A method and apparatus implementing domino static random access memory (SRAM) leakage current reduction include a local evaluation circuit coupled to true and complement bit lines of a pair of local SRAM cell groups, receives precharge signals and provides an output connected to a global dot line. A sleep input is applied to SRAM sleep logic and a write driver including sleep control. Data true and data complement outputs of the write driver are forced to a respective selected level to discharge the bit lines and global dot lines when the sleep input transitions high. Discharging the bit lines and global dot lines is implemented through gating in the write driver without requiring any additional devices in the local evaluation circuit.Type: GrantFiled: May 4, 2007Date of Patent: August 19, 2008Assignee: International Business Machines CorporationInventors: Todd Alan Christensen, Elizabeth Lair Gerhard, Omer Heymann, Amira Rozenfeld
-
Patent number: 7206236Abstract: Arrays such as SRAMs, DRAMs, CAMs & Programmable ROMs having multiple independent failures are repaired using redundant bit lines. A first embodiment provides redundant bit lines on one side of the array. During a write, data is shifted towards the redundant bit lines on the one side of the array, bypassing failed bit lines. A second embodiment provides a spare bit line on each side of the array. During a write, a first failing bit line is replaced by a first spare bit line on a first side of the array, and a second failing bit line is replaced by a second spare bit line on a second side of the array.Type: GrantFiled: January 12, 2006Date of Patent: April 17, 2007Assignee: International Business Machines CorporationInventors: Anthony Gus Aipperspach, Todd Alan Christensen, Elizabeth Lair Gerhard, George Francis Paulik