Patents by Inventor Ellen Chen Yeh

Ellen Chen Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semi-digital delay locked loop circuit and method
    Patent number: 7795937
    Abstract: A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: September 14, 2010
    Assignee: MStar Semiconductor, Inc.
    Inventors: Sterling Smith, Ellen Chen Yeh, Wen cai Lu
  • Semi-Digital Delay Locked Loop Circuit and Method
    Publication number: 20090243679
    Abstract: A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.
    Type: Application
    Filed: March 12, 2009
    Publication date: October 1, 2009
    Applicant: MSTAR SEMICONDUCTOR, INC.
    Inventors: Sterling Smith, Ellen Chen Yeh, Wen cai Lu