Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.

Abstract: A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multilayer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom.

Abstract: A method of forming a semiconductor device is provided, wherein the method includes forming a shaped gate structure over an active region, the shaped gate structure comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, and forming raised source/drain regions adjacent to the gate structure, the raised source/drain regions being formed at opposing sides of the shaped gate structure relative to a length direction of the shaped gate structure, wherein the gate electrode has a tapering shape according to which a dimension of the gate electrode along the length direction varies from a maximum value at a lower portion of the gate electrode close to the gate dielectric layer towards a minimal value at a top portion of the gate electrode.

Abstract: A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including forming a multi-layer stack for an HKMG gate on a substrate, the multilayer stack including a gate electrode layer of amorphous silicon or polycrystalline silicon, forming a patterned hard mask above the gate electrode layer, etching partially into the gate electrode layer through the patterned hard mask to define multiple partially etched gate stacks and a partially etching gate electrode layer, forming a conformal protective layer wrapping over the partially etched gate electrode layer and the patterned hard mask, and etching through a remainder of the partially etched gate electrode layer with the conformal protective layer wrapped over the partially etched gate stacks and the patterned hard mask, as well as an HKMG transistor resulting therefrom.

Abstract: A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

Abstract: An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.

Abstract: A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

Abstract: In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

Abstract: In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor substrate, forming a plurality of trenches in the test region, the trenches of the plurality of trenches having at least one of a varying width, a varying length, and a varying bridge between adjacent trenches, determining depth values of the trenches, and evaluating the risk of defects of gate electrodes to be formed on the basis of the depth values.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Abstract: A method of monitoring critical dimensions of gate electrode structures is provided including providing a substrate, forming a gate electrode pattern on the substrate comprising forming gate electrode lines parallel to each other, forming a mask layer on the gate electrode pattern and forming openings in the mask layer in a crosswise direction with respect to the direction of the parallel gate electrode lines, thereby exposing portions of the gate electrode pattern, etching exposed portions of the gate electrode pattern through the mask layer openings, thereby obtaining a negative image of the mask layer openings, removing remaining portions of the mask layer, and monitoring dimensions of the mask layer openings.

Abstract: The present disclosure describes an apparatus and method for monitoring the environment of a baby, i.e. the outside environment and the direct environment in direct contact with the baby. Environment elements which can be monitored include the temperature, humidity, sunlight intensity and whether or not the environment is damp. Using the temperature and humidity data, the heat index can also be calculated. The child's direct environment is a weighted value which considers the environment elements relating directly to the child and the direct ambient surroundings of the child. This weighted value, for instance, takes into account the skin temperature of the child as well as the ambient temperature, humidity, dampness of the direct surroundings of the child.

Abstract: A semiconductor structure includes a trench isolation structure, a trench capping layer, a gate structure and a sidewall spacer. The trench isolation structure includes a first electrically insulating material. The trench capping layer is provided over the trench isolation structure. The trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The gate structure includes a gate insulation layer including a high-k material and a gate electrode over the gate insulation layer. The gate structure has a first portion over the trench capping layer. The sidewall spacer is provided adjacent the gate structure. A portion of the sidewall spacer is provided on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

Abstract: The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

Abstract: The present disclosure provides, in a first aspect, a semiconductor device structure, including an SOI substrate comprising a semiconductor base substrate, a buried insulating structure formed on the semiconductor base substrate and a semiconductor film formed on the buried insulating structure, wherein the buried insulating structure comprises a multilayer stack having a nitride layer interposed between two oxide layers. The semiconductor device structure further includes a semiconductor device formed in and above an active region of the SOI substrate, and a back bias contact which is electrically connected to the semiconductor base substrate below the semiconductor device.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a capacitor structure comprising an active region formed in a semiconductor substrate, a MOSFET device comprising source and drain regions formed in the active region and a gate electrode formed above the active region, and a first electrode and a second electrode formed in a metallization layer above the MOSFET device, wherein the first electrode is electrically connected with the source and drain regions via respective source and drain contacts and the second electrode is electrically connected with the gate electrode via a gate contact.

Abstract: The present disclosure provides, in accordance with some illustrative embodiments, a method of forming a semiconductor device, the method including providing an SOI substrate with an active semiconductor layer disposed on a buried insulating material layer, which is in turn formed on a base substrate material, forming a gate structure on the active semiconductor layer in an active region of the SOI substrate, partially exposing the base substrate for forming at least one bulk exposed region after the gate structure is formed, and forming a contact structure for contacting the at least one bulk exposed region.

Abstract: A method of forming a gate structure over a hybrid substrate structure with topography having a bulk region and an SOI region is disclosed including forming a gate material layer above the SOI and bulk regions, forming a mask layer above the gate material layer, forming a first planarization layer above the mask layer, forming a first gate structure masking pattern above the first planarization layer, patterning the first planarization layer in alignment with the first gate structure masking pattern, and patterning the mask layer in accordance with the patterned first planarization layer, resulting in a gate mask disposed above the gate material layer.