Patents by Inventor Elmar Gaugler
Elmar Gaugler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8930870Abstract: Optimized buffer placement is provided based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. An estimated slack is calculated for each branch, the branches are arranged according to the calculated slack, decoupling buffers are inserted in all branches except the most critical branch(es), the most critical branch(es) are globally routed and slew conditions are fixed within this branch, and at least one next branch is globally routed and slew conditions are fixed therein.Type: GrantFiled: September 24, 2013Date of Patent: January 6, 2015Assignee: International Business Machines CorporationInventors: Lukas Daellenbach, Elmar Gaugler, Ralf Richter
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Patent number: 8701059Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: GrantFiled: March 1, 2013Date of Patent: April 15, 2014Assignee: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Publication number: 20140019665Abstract: Optimized buffer placement is provided based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. An estimated slack is calculated for each branch, the branches are arranged according to the calculated slack, decoupling buffers are inserted in all branches except the most critical branch(es), the most critical branch(es) are globally routed and slew conditions are fixed within this branch, and at least one next branch is globally routed and slew conditions are fixed therein.Type: ApplicationFiled: September 24, 2013Publication date: January 16, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas DAELLENBACH, Elmar GAUGLER, Ralf RICHTER
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Patent number: 8566774Abstract: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.Type: GrantFiled: November 10, 2011Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Lukas Daellenbach, Elmar Gaugler, Ralf Richter
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Publication number: 20130239075Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: ApplicationFiled: March 1, 2013Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Patent number: 8516417Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: GrantFiled: July 7, 2010Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Patent number: 8423940Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.Type: GrantFiled: August 15, 2011Date of Patent: April 16, 2013Assignee: International Business Machines CorporationInventors: Lukas Daellenbach, Elmar Gaugler, Wilhelm Haller, Ralf Richter
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Publication number: 20130047130Abstract: A computerized method, data processing system and computer program product reduce noise for a buffered design of an electronic circuit which was already placed and routed. For all areas between a power stripe and a ground stripe (half bay) in the design, the shapes are divided in different criticality levels. The shapes are rearranged based on their criticality level such that shapes with higher criticality level are placed closer to the stripes than those with lower criticality level.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: IBM CORPORATIONInventors: Lukas Daellenbach, Elmar Gaugler, Wilhelm Haller, Ralf Richter
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Patent number: 8302056Abstract: The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.Type: GrantFiled: July 7, 2010Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Publication number: 20120151193Abstract: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.Type: ApplicationFiled: November 10, 2011Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lukas DAELLENBACH, Elmar GAUGLER, Ralf RICHTER
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Publication number: 20110035712Abstract: The invention relates to a method and a system for placing macros of a multilevel hierarchical description of a design unit on a chip. The method starts off by repartitioning the macro structure of the design unit into a set of latch macros and a set of combinatorial macros. By definition, a combinatorial macro is constructed in such a way that it contains no latches, and a latch macro contains latches and is constructed in such a way that each primary input/output of the latch macro coincides with an input or an output of a latch within said latch macro. After repartitioning the macro structure, the latch macros are synthesized within temporary boundaries and placed on the chip. Subsequently, the combinatorial macros are sequentially placed within a temporary boundary and synthesized one by one.Type: ApplicationFiled: July 7, 2010Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler
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Publication number: 20110035711Abstract: The invention relates to a method and a system for repartitioning a formalized hardware description of a hierarchically structured electronic circuit design unit comprising a plurality of macros in terms of latch macros and combinatorial macros. In a first step, each macro is dissected into latch macros and signal cones in such a way that each signal cone comprises signals linking macro input/output to a latch output/input, and each latch macro comprises at least one latch, each primary input an output of said latch macro coinciding with an input or an output of a latch within said latch macro. Subsequently, combinatorial macros are created by merging combinatorial signal cones along unit signal paths.Type: ApplicationFiled: July 7, 2010Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Elmar Gaugler, Wilhelm Haller, Friedhelm Kessler