Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract: A fuse-redundancy circuit for use in an integrated circuit and method for operating the same. The fuse-redundancy circuit comprises at least two fuses, at least two fuse-control devices, and a status-checking circuit. Each one of the at least two fuse-control devices is operable to control an electric current flowing through a corresponding one of the at least two fuses. The status-checking circuit operable to generate a status signal having (i) a first state when at least one of the at least two fuses is blown, and (ii) a second state otherwise.

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Abstract: A CMOS device architecture which includes substrate-gated inverted PMOS transistors, as well as bulk NMOS. The inverted-PMOS channels are formed in a different layer from the NMOS gates, and these layers may even have different compositions. Moreover, the NMOS and inverted-PMOS devices have different gate oxide layers, so the thicknesses can be independently optimized. The drain underlap of the inverted device is defined by a patterning step, so it can be increased for high-voltage operation if desired.

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active region in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Abstract: A semiconductor read only memory device includes memory cells arranged in a matrix of rows and columns; word lines crossing the matrix, wherein one word line is connected to each row of memory cells; and bit lines interdigitated with column lines and positioned such that each column of memory cells is between a bit line and a column line. The matrix is subdivided into cells, where each cell has four memory cells arranged symmetrically about a bit line in two rows and two columns. All four of the cells are connected to the bit line at a common electrical node, wherein selected cells are connected to a column line. The memory device also includes a row select driver for selecting memory cells in a single row; a column select driver for selecting a single column line; and circuitry for selecting one of the bit lines adjacent to a column line.

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SPRAM cells.

Abstract: An MOS integrated circuit includes internal circuitry for detecting the voltage level of an external power supply. The internal circuitry comprises networks for producing two reference voltages, each of which varies with supply voltage in a different but predictable manner such that when the reference voltages are equal, the supply voltage is at a sufficiently high level to assure the generation of valid logic levels. As the supply voltage increases beyond such level, the two reference voltages diverge in value, detection of which is achieved with a different amplifier. Circuitry responsive to the output of the differential amplifier gives a positive indication of sufficient supply voltage to other circuit portions of the integrated circuit device.