Patents by Inventor Ely K. Tsern
Ely K. Tsern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955165Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.Type: GrantFiled: November 22, 2021Date of Patent: April 9, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, John E. Linstadt, Thomas A. Giovannini, Scott C. Best, Kenneth L Wright
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Publication number: 20240070000Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.Type: ApplicationFiled: August 14, 2023Publication date: February 29, 2024Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
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Patent number: 11914508Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.Type: GrantFiled: October 7, 2020Date of Patent: February 27, 2024Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern
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Patent number: 11775369Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.Type: GrantFiled: February 28, 2020Date of Patent: October 3, 2023Assignee: Rambus Inc.Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
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Publication number: 20220148643Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.Type: ApplicationFiled: November 22, 2021Publication date: May 12, 2022Inventors: Frederick A. Ware, Ely K. Tsern, John E. Linstadt, Thomas A. Giovannini, Scott C. Best, Kenneth L. Wright
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Patent number: 11232827Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.Type: GrantFiled: September 11, 2020Date of Patent: January 25, 2022Assignee: Highlands, LLCInventors: Craig E. Hampel, Richard E. Perego, Stefanos Sidiropoulos, Ely K. Tsern, Frederick A. Ware
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Patent number: 11211114Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.Type: GrantFiled: July 3, 2019Date of Patent: December 28, 2021Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, John E. Linstadt, Thomas J. Giovannini, Scott C. Best, Kenneth L. Wright
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Publication number: 20210280226Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.Type: ApplicationFiled: March 24, 2021Publication date: September 9, 2021Inventors: Frederick A. Ware, Ely K. Tsern
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Publication number: 20210098280Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.Type: ApplicationFiled: October 12, 2020Publication date: April 1, 2021Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
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Publication number: 20210098048Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.Type: ApplicationFiled: September 11, 2020Publication date: April 1, 2021Inventors: Craig E. HAMPEL, Richard E. PEREGO, Stefanos SIDIROPOULOS, Ely K. TSERN, Frederick A. WARE
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Patent number: 10964361Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.Type: GrantFiled: December 11, 2017Date of Patent: March 30, 2021Assignee: RAMBUS INC.Inventors: Frederick A. Ware, Ely K. Tsern
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Publication number: 20210073122Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.Type: ApplicationFiled: October 7, 2020Publication date: March 11, 2021Inventors: Frederick A. Ware, Ely K. Tsern
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Publication number: 20210027825Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.Type: ApplicationFiled: June 8, 2020Publication date: January 28, 2021Inventors: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel
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Publication number: 20200349991Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: ApplicationFiled: April 20, 2020Publication date: November 5, 2020Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty
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Patent number: 10817419Abstract: A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory.Type: GrantFiled: January 11, 2019Date of Patent: October 27, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern
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Patent number: 10811080Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.Type: GrantFiled: December 10, 2018Date of Patent: October 20, 2020Assignee: Rambus Inc.Inventors: Craig E. Hampel, Richard E. Perego, Stefanos Sidiropoulos, Ely K. Tsern, Frederick A. Ware
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Patent number: 10804139Abstract: This application is directed to a system including a plurality of devices that are stacked one on top of another. Each device includes a substrate having two opposing surfaces. A first row of contacts is coupled on a first surface and includes a first contact and a second contact that are adjacent to each other. A second row of contacts is coupled on a respective second surface and includes a third contact. Each contact in the second row of contacts is physically aligned with an opposite contact in the first row. The third contact is disposed opposite and physically aligned with the first contact in the first row, and electrically coupled to the second contact in the first row. Operational circuitry is electrically coupled to at least the first contact on the first row, and at least two of the plurality of devices have distinct operational circuitry.Type: GrantFiled: November 28, 2017Date of Patent: October 13, 2020Assignee: RAMBUS INC.Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
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Publication number: 20200264943Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.Type: ApplicationFiled: February 28, 2020Publication date: August 20, 2020Inventors: Ely K. Tsern, Mark A. Horowitz, Frederick A. Ware
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Patent number: 10706910Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.Type: GrantFiled: February 25, 2019Date of Patent: July 7, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, Richard E. Perego, Craig E. Hampel
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Patent number: 10650872Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.Type: GrantFiled: December 10, 2018Date of Patent: May 12, 2020Assignee: Rambus Inc.Inventors: Frederick A. Ware, Ely K. Tsern, Brian S. Leibowitz, Wayne Frederick Ellis, Akash Bansal, John Welsford Brooks, Kishore Ven Kasamsetty