Abstract: A robust multichannel SPR instrument with exceptionally high sensitivity (<pg/mm2). The instrument utilizes an SPR detection scheme providing multiple reflections from a planar light guide configuration to amplify the reflected light intensity changes near the resonance angle. This SPR approach is amenable to simultaneous multichannel detection while maintaining high sensitivity with a simple, cost-effective design. The idea of using multiple reflections to excite multiple surface plasmon waves seems counterintuitive at first because the SPR resonance will be broadened; the broadened resonance will diminish sensitivity for angle or wavelength detection modes. However, changes in reflected light intensity near the resonance angle will be amplified by the multiple reflections, thereby increasing the sensitivity of SPR utilizing intensity detection at a fixed angle of incidence.

Abstract: A robust multichannel SPR instrument with exceptionally high sensitivity (<pg/mm2). The instrument utilizes an SPR detection scheme providing multiple reflections from a planar light guide configuration to amplify the reflected light intensity changes near the resonance angle. This SPR approach is amenable to simultaneous multichannel detection while maintaining high sensitivity with a simple, cost-effective design. The idea of using multiple reflections to excite multiple surface plasmon waves seems counterintuitive at first because the SPR resonance will be broadened; the broadened resonance will diminish sensitivity for angle or wavelength detection modes. However, changes in reflected light intensity near the resonance angle will be amplified by the multiple reflections, thereby increasing the sensitivity of SPR utilizing intensity detection at a fixed angle of incidence.

Abstract: A method that uses effective widths of NMOS and PMOS devices in a digital circuit and their intrinsic junction and subthreshold leakage currents to produce a specification for IDDQ, the range of IDDQ, and the delta of IDDQ between pre- and post-overvoltage stress tests to screen out defective integrated circuits having excessive extrinsic current leakage. The present invention provides for a computer-implemented method that generates an indication of whether IDDQ values associated with integrated circuits that have been tested are within the IDDQ specification or not. This processing eliminates the need for time-intensive and costly burn-in testing on the integrated circuits.

Abstract: A process for metallizing semiconductor devices is provided, wherein a plurality of aluminum contacts is formed. The plurality of aluminum contacts is at least partially nitrided in a nitrogen-containing plasma at a temperature of less than about 350.degree. C. The aluminum nitride layer or cap is capable of eliminating aluminum corrosion without affecting the electrical properties of the aluminum contacts.