Abstract: When using membrane key pads, it is often desirable to provide the user with a sense that contact has been made. In this regard, there is disclosed a 1 KHz 4-bit counter which is normally held at a count just beyond the place where "ones" appear in the third bit position. When it is desired to provide an audio click, the processor resets the counter to zero and then releases the counter. The "ones" in the third bit position, which occur in four consecutive counts, control the application of the 1 KHz frequency to the mechanical sounder. By connecting the fourth bit position to the synchronous reset input, the counter stops incrementing after the four consecutive "ones" and waits for the next reset by the processor.

Abstract: There is disclosed a processor controlled digital communication device which accepts message commands from a communication system as part of a communication protocol. These command messages are stripped from the protocol and combined within the communication device to control signaling thereat. Multi-bit time separated information (I) fields are used together with a single bit signaling (S) field. The S field bits are compiled over several frames to become the command messages.

Abstract: A full duplex, synchronous data set (10) includes primary signal processing circuitry which generates a modulated transmit data signal in response to serial data from a terminal interface (17). The modulated data signal is transmitted over a primary channel of a transmit line (11). The primary signal processing circuitry also receives modulated data signals from a primary channel of a receive line (12) and recovers therefrom a serial bit stream for presentation to the interface. The operating parameters of the primary signal processing circuitry are specified by a primary controller (30) over a plurality of buses (PA, PC, PD). The primary controller includes a microprocessor (310) and associated peripherals (315, 320, 325, 330, 335). The data set also includes secondary signal processing circuitry (40) which transmits and receives diagnostic and control information over respective secondary channels of the transmit line and receive lines.

Abstract: A full duplex, synchronous data set (10) includes primary signal processing circuitry which generates a modulated transmit data signal in response to serial data from a terminal interface (17). The modulated data signal is transmitted over a primary channel of a transmit line (11). The primary signal processing circuitry also receives modulated data signals from a primary channel of a receive line (12) and recovers therefrom a serial bit stream for presentation to the interface. The operating parameters of the primary signal processing circuitry are specified by a primary controller (30) over a plurality of buses (PA, PC, PD). The primary controller includes a microprocessor (310) and associated peripherals (315, 320, 325, 330, 335). The data set also includes secondary signal processing circuitry (40) which transmits and receives diagnostic and control information over respective secondary channels of the transmit line and receive lines.