Patents by Inventor Emanuele Lopelli
Emanuele Lopelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967983Abstract: Aspects described herein include devices and methods for smart ultra wideband transmissions. In one aspect, an apparatus includes pulse generation circuitry configured to output a plurality of transmission (TX) pulse samples at a selected signal sample rate, where each pulse sample of the plurality of TX pulse samples comprises a value associated with a pulse amplitude at a corresponding sample time The apparatus includes a plurality of power amplifier (PA) cells, with each PA cell of the plurality of PA cells comprising a corresponding current source and associated gates, and where the associated gates of a PA cell are selectable to configure an on state and an off state. Logic circuitry of the apparatus is configured to set the on state or the off state for each PA cell.Type: GrantFiled: September 22, 2022Date of Patent: April 23, 2024Assignee: QUALCOMM IncorporatedInventors: Yi Zeng, Cheng-Han Wang, Emanuele Lopelli, Chan Hong Park, Liang Zhao, Le Nguyen Luong, Koorosh Akhavan
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Publication number: 20240106496Abstract: Aspects described herein include devices and methods for smart ultra wideband transmissions. In one aspect, an apparatus includes pulse generation circuitry configured to output a plurality of transmission (TX) pulse samples at a selected signal sample rate, where each pulse sample of the plurality of TX pulse samples comprises a value associated with a pulse amplitude at a corresponding sample time The apparatus includes a plurality of power amplifier (PA) cells, with each PA cell of the plurality of PA cells comprising a corresponding current source and associated gates, and where the associated gates of a PA cell are selectable to configure an on state and an off state. Logic circuitry of the apparatus is configured to set the on state or the off state for each PA cell.Type: ApplicationFiled: September 22, 2022Publication date: March 28, 2024Inventors: Yi ZENG, Cheng-Han WANG, Emanuele LOPELLI, Chan Hong PARK, Liang ZHAO, Le Nguyen LUONG, Koorosh AKHAVAN
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Publication number: 20240080062Abstract: An apparatus includes a low-noise amplifier having an input and an output, a first switch coupled between the input of the low-noise amplifier and the output of the low-noise amplifier, and a transformer including a first inductor and a second inductor, wherein the first inductor is coupled to the output of the low-noise amplifier. The apparatus also includes a power amplifier having an input and an output, and a switching circuit coupled between the output of the power amplifier and the second inductor.Type: ApplicationFiled: September 7, 2022Publication date: March 7, 2024Inventors: Cheng-Han WANG, Yi ZENG, Takahide NISHIO, Chan Hong PARK, Emanuele LOPELLI, Liang ZHAO
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Patent number: 11695372Abstract: Apparatus and methods for generating multiple oscillating signals. An example circuit generally includes a first voltage-controlled oscillator (VCO) circuit and a second VCO circuit having a differential bias input coupled to a differential output of the first VCO circuit. At least one of the first VCO circuit or the second VCO circuit generally includes: a pair of cross-coupled transistors comprising a first transistor and a second transistor, a first inductive element coupled between a first node and the drain of the first transistor, a second inductive element coupled between the first node and the drain of the second transistor, a third transistor having a drain coupled to the drain of the first transistor and having a source coupled to a second node, and a fourth transistor having a drain coupled to the drain of the second transistor and having a source coupled to the second node.Type: GrantFiled: February 11, 2022Date of Patent: July 4, 2023Assignee: QUALCOMM IncorporatedInventors: Emanuele Lopelli, Cheng-Han Wang, Yi Zeng
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Patent number: 11032113Abstract: Examples herein disclose apparatus and systems for hybrid vector based polar modulator schemes that may use a series of polar modulators to create a system of vector modulators. The resulting polar response may be de-composed into the sum of the polar modulators. This approach allows accurate phase modulation in two such links without the need for high resolution AM part to cover the IQ plane of a QAM modulator.Type: GrantFiled: September 25, 2018Date of Patent: June 8, 2021Assignee: QUALCOMM INCORPORATEDInventors: Magnus Olov Wiklund, Emanuele Lopelli
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Patent number: 10771234Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.Type: GrantFiled: September 28, 2018Date of Patent: September 8, 2020Assignee: QUALCOMM IncorporatedInventors: Emanuele Lopelli, Magnus Olov Wiklund, Charles Chang-I Wang, Salvatore Pennisi, Richard McConnell
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Patent number: 10644926Abstract: Methods, systems, and devices for wireless communications are described. The method may include identifying phase information generated from modulation information, mapping the phase information by mapping a second phase point located in a second quadrant to a first phase point of a first quadrant, where the first phase point may be associated with a phase trajectory of the phase information, synthesizing the mapped phase information associated with the phase trajectory based on mapping the phase information, rotating the phase trajectory based on a phase-plane rotation value associated with mapping the phase information, and generating a modulated signal associated with a carrier frequency based on mapping the phase information and rotating the phase trajectory.Type: GrantFiled: April 25, 2019Date of Patent: May 5, 2020Assignee: QUALCOMM IncorporatedInventors: Emanuele Lopelli, Magnus Olov Wiklund, Salvatore Pennisi
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Publication number: 20200106599Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may receive an otw signal that is associated with low-path pass information and transmission data. The apparatus may apply a cost function and an update function to the otw signal prior to sending the otw signal to an oscillator. The apparatus may determine a correction factor for use in estimating a gain of the oscillator based at least in part on an output of the update function.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Inventors: Emanuele LOPELLI, Magnus Olov WIKLUND, Charles Chang-I WANG, Salvatore PENNISI, Richard MCCONNELL
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Publication number: 20200099558Abstract: Examples herein disclose apparatus and systems for hybrid vector based polar modulator schemes that may use a series of polar modulators to create a system of vector modulators. The resulting polar response may be de-composed into the sum of the polar modulators. This approach allows accurate phase modulation in two such links without the need for high resolution AM part to cover the IQ plane of a QAM modulator.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: Magnus Olov WIKLUND, Emanuele LOPELLI
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Publication number: 20180175867Abstract: A method for correcting deterministic jitter in an all-digital phase-locked loop (ADPLL) is described. The method includes determining an offset to an input frequency of the ADPLL that causes an oscillator tuning word (OTW) provided to a digitally-controlled oscillator (DCO) quantizer to fall between two DCO codes. The method also includes applying the offset to the input frequency of the ADPLL to force the DCO quantizer to have gain.Type: ApplicationFiled: December 16, 2016Publication date: June 21, 2018Inventors: Emanuele Lopelli, Charles Wang, Elias Dagher
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Publication number: 20170371990Abstract: A method of calibrating an All-Digital Phase Locked Loop (ADPLL) includes obtaining a model of the ADPLL and applying an input signal to both the ADPLL and to the model. The ADPLL generates an actual output of the ADPLL, while the model generates a model output. An error between the actual output of the ADPLL and the model output is then sensed. The method also includes generating a calibration value based on the error between the actual output of the ADPLL and the model output, and adjusting a feedforward gain of the ADPLL based on the calibration value.Type: ApplicationFiled: June 24, 2016Publication date: December 28, 2017Inventors: Magnus Olov WIKLUND, Emanuele LOPELLI, Charles WANG
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Patent number: 9806880Abstract: An example phase-locked loop (PLL) includes a digital filter, an oscillator, and a time-to-digital converter (TDC). The digital filter is configured to sample at a discrete time that is responsive to a reference clock signal received at the digital filter. The oscillator is coupled to the digital filter and configured to generate an output signal of the PLL. The TDC is coupled to the oscillator to determine a phase difference between the output signal and the reference clock signal. The TDC also provides a time signal to the digital filter that is based on the phase difference and is representative of an instantaneous rate of operation of the PLL. The digital filter is further configured to adjust a response characteristic of the digital filter according to the time signal.Type: GrantFiled: June 15, 2016Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Magnus Olov Wiklund, Emanuele Lopelli, Charles Wang, Mahbod Mofidi
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Publication number: 20170134030Abstract: Disclosed are methods and apparatuses for reducing fractional spurs in an All-Digital Phase Lock Loop (ADPLL). An exemplary apparatus includes a crystal oscillator configured to generate a first frequency reference signal, a non-integer divider coupled to the crystal oscillator and configured to divide the first frequency reference signal by a non-integer variable to generate a second frequency reference signal, and a multiplexor coupled to the non-integer divider and the crystal oscillator and configured to output the first frequency reference signal or the second frequency reference signal to the ADPLL, wherein the multiplexor is configured to output the second frequency reference signal based on the ADPLL being tuned to a low fractionality channel.Type: ApplicationFiled: May 24, 2016Publication date: May 11, 2017Inventors: Mahbod MOFIDI, Emanuele LOPELLI, Magnus Olov WIKLUND, Charles WANG
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Patent number: 9459292Abstract: Aspects of the present disclosure are generally directed to techniques and apparatus for estimating a gain of a VCO in a PLL. In certain aspects, the technique includes calculating a C-V characteristic of a varactor matched to another varactor in the VCO. The technique also includes estimating the gain of the VCO based on the C-V characteristic of the varactor, a tank inductance of the VCO, and an output frequency of the VCO. Aspects of the present disclosure allow for estimating the gain of the VCO while the PLL remains in operation.Type: GrantFiled: March 20, 2014Date of Patent: October 4, 2016Assignee: QUALCOMM INCORPORATEDInventors: Emanuele Lopelli, Charles Chang-I Wang, Salvatore Pennisi, Shervin Moloudi
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Publication number: 20150268279Abstract: Estimating a gain of a VCO in a PLL, including: means for matching to a varactor in the VCO; and means for estimating the gain of the VCO by calculating a C-V characteristic of the means for matching along with tank inductance and an output frequency of the VCO, wherein estimating the gain of the VCO by calculating the C-V characteristic of the means for matching allows the PLL to remain in operation during estimation.Type: ApplicationFiled: March 20, 2014Publication date: September 24, 2015Applicant: QUALCOMM INCORPORATEDInventors: Emanuele LOPELLI, Charles Chang-I WANG, Salvatore PENNISI, Shervin MOLOUDI
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Patent number: 7738618Abstract: The present invention relates to a multiband PLL arrangement comprising a single loop PLL with a phase/frequency detecting means (1), a loop filter means (2) and a Voltage Controlled Oscillator (VCO) (3), to which PLL a reference voltage signal (Vref) is input. It further comprises a control circuit for appropriately locking the VCO (3) to the correct frequency band, said control circuit comprising a multi-window circuit (4) with at least first and second window amplitudes each defined by respective upper and lower voltage levels, and comparing means (5A, 5B) are provided for comparing a first VCO control voltage output from the loop filter means (2) with the upper and lower voltage levels of a first, broadest amplitude window.Type: GrantFiled: October 23, 2003Date of Patent: June 15, 2010Assignee: Telefonaktiebolaget L M Ericsson (publ)Inventors: Harald Jacobsson, Emanuele Lopelli
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Publication number: 20090141825Abstract: The present invention relates to a multiband PLL arrangement comprising a single loop PLL, with a phase/frequency detecting means (1), a loop filter means (2) and a Voltage Controlled Oscillator (VCO) (3), to which PLI a reference voltage signal (Vref) is input. It further comprises a control circuit for appropriately locking the VCO (3) to the correct frequency band, said control circuit comprising a multi-window circuit (4) with at least first and second window amplitudes each defined by respective upper and lower voltage levels, and comparing means (5A, 5B) are provided for comparing a first VCO control voltage output from the loop filter means (2) with the upper and lower voltage levels of a first, broadest amplitude window.Type: ApplicationFiled: October 23, 2003Publication date: June 4, 2009Applicant: Telefonaktiebolaget L M Ericson (publ)Inventors: Harald Jacobsson, Emanuele Lopelli