Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.

Abstract: A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.

Abstract: When designing an electronic circuit to be implemented on an integrated circuit die which includes several metal layers, a technology-independent description of a system is generated, the technology-independent description specifying a signal and a selected metal layer for the signal. Also, an electronic circuit description of a system is synthesized from a technology-independent description of the system. Specifically, a technology-independent description of the system is input, the technology-independent description specifying a signal and a metal layer attribute for the signal. Electronic components are selected from a library based on the technology-independent description and interconnections between the electronic components are specified. A metal layer is then specified for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

Abstract: A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.

Abstract: An on-chip misalignment indicator for measuring misalignment between layers of an integrated circuit die employs a first contact, and a second contact. A current path between the first and second contacts having a resistance that varies as a function of misalignment between successive layers of the integrated circuit die. Similarly, a method for detecting misalignment between layers of an integrated circuit die involves passing and measuring a current between a first contact. The amount of the current being indicative of an amount of misalignment between layers of the integrated circuit die.

Abstract: A computer-based test method and apparatus for measuring DC current drawn by an integrated circuit. The apparatus has a plurality of current measurement ranges and is first initialized to a selected one of the measurement ranges. Next, the apparatus measures the DC current drawn by the integrated circuit in the selected measurement range and increments the selected measurement range if the measured DC current is out of the selected measurement range. The apparatus repeats the steps of measuring and incrementing until the measured DC current is in the selected measurement range. The measured DC current is then compared to a specification limit for the integrated circuit.

Abstract: A method for removing solder from the leads of ICs including immersing the IC in an acid solution. The acid solution dissolves the excess solder on the IC leads. The acid solution is preferably a hydrogen chloride solution containing about 38% hydrogen chloride and 62% water. The acid solution, however, can contain up to 50% hydrogen chloride. After the IC is immersed for a period of time, preferably ten minutes, it is removed from the acid solution and rinsed with water. The IC is rinsed so as to remove any remaining acid solution residue. Rinsing for 5 minutes or more typically ensures removing all of the acid solution. The IC is then inspected to determine whether substantially all of the excess solder is removed from the IC leads. If excess solder still remains on the IC leads, the IC is reintroduced into the solder removing process including immersing the IC in the acid solution, rinsing the IC with water, and inspecting the IC.

Abstract: Magnetic sensors are positioned adjacent a semiconductor integrated circuit under test while the circuit is subjected to selected electrical stimuli for purposes of failure analysis. The magnetic image data can be acquired from one or more selected locations about the circuit without any physical connection. By comparing the magnetic sensor information to a predetermined database of magnetic information acquired from known devices, failure modes can be identified. Conventional tester equipment can be used for providing the electrical stimuli to the device under test.

Abstract: In a semiconductor integrated circuit, I/O buffer circuits that include ESD protection are generally provided for each I/O pad. According to the invention, unused pads, i.e. pads that are not connected to core circuitry according to an initial design, are connected to other pads that are used for connection to the core circuitry, thereby employing the unused pads to improve ESD protection of susceptible pads. This approach has the advantages of greater ESD protection without increasing silicon area and without adding any additional steps to the usual fabrication process. The inventive concept is especially useful for augmenting ESD protection of corner pads without requiring new or custom ESD protection circuits. This invention can be easily implemented into known layout tools.

Abstract: A method of testing a semiconductor device includes generating a current waveform for the semiconductor device by measuring the response of the device to an initializing vector group and comparing the current waveform to a golden waveform to determine whether the semiconductor device is good or defective. Apparatus for testing the semiconductor device includes a vector generator providing an initialization vector group to the semiconductor device, a measurement unit for measuring a plurality of current measurements from the semiconductor device which responds to the input of the initialization vector group, a generation unit for generating a current waveform from the current measurements of the semiconductor device, and an analysis unit for comparing the current waveform to a golden waveform to determine whether the device falls outside a tolerance margin of the golden waveform.

Abstract: Semiconductor integrated circuits are electrically marked at final test time to form a permanent, visually and electrically readable record of the test results. The electrical record can provide a simple good/bad indication, i.e. indicate whether or not the device passed final test. This provides for more efficient handling of failed devices returned from the field, as the manufacturer can immediately determine whether the device in question passed final test before shipment--or inadvertently "escaped" from the manufacturer. The electrical marking technique, preferably using one or more fuses on board the device, can be used to record quiescent current test, speed sort test and various other final test results. These and other test results recorded on the chip are useful to quality and reliability studies, and in reducing the time and effort required to determine the failure mode of a returned device.

Abstract: Special probe pads are formed within the core of an integrated circuit, such as an ASIC, to provide direct access to internal circuitry for conducting failure analysis. For example, internal probe pads can be provided around an embedded RAM core for bit mapping the RAM core if necessary. An improved probe card is described to provide for accessing these internal probe pads using automated probing machines. The internal probe pads, preferably smaller in size than wire bonding pads, are located in available interstices on the die, preferably without increasing silicon area. Multiplexers can be used to isolate these probe pads during normal operation of the integrated circuit.

Abstract: An on-chip misalignment indicator for measuring misalignment between layers of an integrated circuit die employs a first contact, and a second contact. A current path between the first and second contacts has a resistance that varies as a function of misalignment between successive layers of the integrated circuit die. Similarly, a method for detecting misalignment between layers of an integrated circuit die involves passing and measuring a current between a first contact and a second contact. The amount of the current is indicative of an amount of misalignment between layers of the integrated circuit die.