Patents by Inventor Emesahw Ashenafi

Emesahw Ashenafi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power gating circuit utilizing double-gate fully depleted silicon-on-insulator transistor
    Patent number: 10469076
    Abstract: Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold voltage to eliminate the need for standalone sleep transistors.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 5, 2019
    Assignee: The Curators of the University of Missouri
    Inventors: Masud H. Chowdhury, Emesahw Ashenafi
  • POWER GATING CIRCUIT UTILIZING DOUBLE-GATE FULLY DEPLETED SILICON-ON-INSULATOR TRANSISTOR
    Publication number: 20180145685
    Abstract: Combining the functionality of sleep transistors with logic devices in power-gating circuits by utilizing fully depleted silicon-on-insulator (FDSOI) transistors. In an embodiment, a back gate of a FDSOI transistor controls the threshold voltage to eliminate the need for standalone sleep transistors.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 24, 2018
    Applicant: The Curators of the University of Missouri
    Inventors: Masud H. Chowdhury, Emesahw Ashenafi