Patents by Inventor Emily R. Kinser
Emily R. Kinser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8569154Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.Type: GrantFiled: March 16, 2012Date of Patent: October 29, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
-
Patent number: 8563423Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.Type: GrantFiled: July 27, 2011Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser
-
Publication number: 20130273743Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.Type: ApplicationFiled: June 12, 2013Publication date: October 17, 2013Inventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
-
Patent number: 8546961Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.Type: GrantFiled: January 10, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William F. Landers, Kevin S. Petrarca, Richard P. Volant, Kevin R. Winstel
-
Publication number: 20130244420Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.Type: ApplicationFiled: May 9, 2013Publication date: September 19, 2013Applicant: International Business Machines CorporationInventors: Paul S. Andry, Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser, Cornelia K. Tsang, Richard P. Volant
-
Publication number: 20130237054Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.Type: ApplicationFiled: April 26, 2013Publication date: September 12, 2013Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
-
Patent number: 8492252Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.Type: GrantFiled: March 16, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
-
Patent number: 8487425Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.Type: GrantFiled: June 23, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Paul S Andry, Mukta G Farooq, Robert Hannon, Subramanian S Iyer, Emily R Kinser, Cornelia K Tsang, Richard P Volant
-
Patent number: 8486814Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.Type: GrantFiled: July 21, 2011Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
-
Publication number: 20130119509Abstract: In one embodiment, the invention provides a back-end-of-line (BEOL) line fuse structure. The BEOL line fuse structure includes: a line including a plurality of grains of conductive crystalline material; wherein the plurality of grains in a region between the first end and a second end include an average grain size that is smaller than a nominal grain size of the plurality of grains in a remaining portion of the line.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MUKTA G. FAROOQ, Emily R. Kinser
-
Patent number: 8415238Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, etching the exposed planar area to form a cavity having a first depth in the structure, removing a second portion of the photoresist to expose a second planar area on the substrate layer, forming a doped portion in the second planar area, and etching the cavity to expose a first conductor in the structure and the doped portion to expose a second conductor in the structure.Type: GrantFiled: January 14, 2010Date of Patent: April 9, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
-
Publication number: 20130069062Abstract: A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits.Type: ApplicationFiled: September 15, 2011Publication date: March 21, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhavana Bhoovaraghan, Mukta G. Farooq, Emily R. Kinser, Sudesh Saroop
-
Patent number: 8399180Abstract: A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.Type: GrantFiled: January 14, 2010Date of Patent: March 19, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, Ramona Kei, Emily R. Kinser, Anthony D. Lisi, Richard Wise, Hakeem Yusuff
-
Publication number: 20130020682Abstract: A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.Type: ApplicationFiled: July 21, 2011Publication date: January 24, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jennifer C. Clark, Emily R. Kinser, Ian D. Melville, Candace A. Sullivan
-
Publication number: 20120326309Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.Type: ApplicationFiled: June 23, 2011Publication date: December 27, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: PAUL S ANDRY, Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Emily R. Kinser, Cornelia K. Tsang, Richard P. Volant
-
Publication number: 20120190189Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.Type: ApplicationFiled: March 16, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
-
Publication number: 20120190196Abstract: A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer, forming doped portions of the substrate layer in the first planar area, removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer, and etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure.Type: ApplicationFiled: March 16, 2012Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, Emily R. Kinser, Richard Wise, Hakeem Yusuff
-
Publication number: 20120175789Abstract: Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.Type: ApplicationFiled: January 10, 2011Publication date: July 12, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Troy L. Graves-Abe, Robert Hannon, Emily R. Kinser, William F. Landers, Kevin S. Patrarca, Richard P. Volant, Kevin R. Winstel
-
Publication number: 20120168952Abstract: Disclosed is a process of making a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. There may also be a cap layer over the copper plug to protect it from oxidation. There may also be a dielectric layer over the cap layer.Type: ApplicationFiled: March 12, 2012Publication date: July 5, 2012Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser, Ian D. Melville, Krystyna W. Semkow
-
Publication number: 20110281432Abstract: A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.Type: ApplicationFiled: July 27, 2011Publication date: November 17, 2011Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, Emily R. Kinser