Patents by Inventor Emmanuel Josse
Emmanuel Josse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352513Abstract: The present description concerns a manufacturing method comprising the following steps: providing a silicon substrate having a via penetrating into the substrate from its front surface and comprising a silicon conductive core and a silicon oxide insulating sheath; etching the substrate from its rear surface, selectively over the sheath so that a portion of said at least one via protrudes from the rear surface; depositing a silicon oxide insulating layer on the rear surface; polishing the insulating layer to expose the core while leaving in place a portion of the thickness of the insulating layer; and forming a conductive electrode in contact with the core.Type: ApplicationFiled: April 19, 2023Publication date: November 2, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Alain INARD, Emmanuel JOSSE
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Publication number: 20230317748Abstract: An imaging device includes an array of photosensors. A film of semiconductor nanoparticles is common to the photosensors of the array. The nanoparticles are configured to be excited by light with wavelengths in a range from 280 to 1500 nanometers. Each photosensor includes a top electrode and a bottom electrode positioned on opposite sides of the film of semiconductor nanoparticles. At least some of the photosensors further include a filter configured to transmit light with wavelengths in a range from 280 to 400 nanometers, and to at least partially filter out light with wavelengths greater than 400 nanometers from reaching the photosensor. A transistor level is electrically coupled to the top and bottom electrodes of the photosensors.Type: ApplicationFiled: April 3, 2023Publication date: October 5, 2023Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Alps) SASInventors: Jonathan STECKEL, Emmanuel JOSSE, Eric MAZALEYRAT, Youness RADID
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Publication number: 20230109590Abstract: A phase change filter is formed by an arrangement of dots, wherein each dot is made of a phase change material. A heating layer of electrically conductive material extends under the arrangement of dots. Current passing through the heating layer changes the dots between two states to alter attenuation of light passing through the filter.Type: ApplicationFiled: October 3, 2022Publication date: April 6, 2023Applicant: STMicroelectronics (Crolles 2) SASInventors: Marios BARLAS, Kirill SHIIANOV, Emmanuel JOSSE, Stephane MONFRAY
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Patent number: 9876032Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: GrantFiled: October 18, 2016Date of Patent: January 23, 2018Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
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Publication number: 20170288664Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.Type: ApplicationFiled: June 22, 2017Publication date: October 5, 2017Inventors: Alexandre Dray, Emmanuel Josse
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Patent number: 9735772Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.Type: GrantFiled: September 25, 2015Date of Patent: August 15, 2017Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Alexandre Dray, Emmanuel Josse
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Publication number: 20170117296Abstract: A device includes both low-voltage (LV) and high-voltage (HV) metal oxide semiconductor (MOS) transistors of opposite types. Gate stacks for the transistors are formed over a semiconductor layer. First spacers made of a first insulator are provided on the gate stacks of the LV and HV MOS transistors. Second spacers made of a second insulator are provided on the gate stacks of the HV MOS transistors only. The insulators are selectively removed to expose the semiconductor layer. Epitaxial growth of semiconductor material is made from the exposed semiconductor layer to form raised source-drain structures that are separated from the gate stacks by the first spacers for the LV MOS transistors and the second spacers for the HV MOS transistors.Type: ApplicationFiled: October 18, 2016Publication date: April 27, 2017Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Sonarith Chhun, Emmanuel Josse, Gregory Bidal, Dominique Golanski, Francois Andrieu, Jerome Mazurier, Olivier Weber
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Patent number: 9543214Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.Type: GrantFiled: October 28, 2014Date of Patent: January 10, 2017Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS, INC.Inventors: Denis Rideau, Elise Baylac, Emmanuel Josse, Pierre Morin, Olivier Nier
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Publication number: 20160134282Abstract: An integrated circuit includes at least one integrated cell disposed at a location of the integrated circuit. The at least one integrated cell may have two integrated devices coupled to at least one site of the integrated cell and a multiplexer, and the two integrated devices respectively oriented in two different directions of orientation. A first integrated device of the two integrated devices that is oriented in one of the two directions of orientation is usable. The integrated circuit may include a controller configured to detect the direction of orientation which, having regard to the disposition of the integrated cell at the location, may allow the first integrated device to be usable, and to control the multiplexer to couple the first integrated device electrically to the at least one site.Type: ApplicationFiled: September 25, 2015Publication date: May 12, 2016Inventors: Alexandre DRAY, Emmanuel Josse
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Patent number: 9318372Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.Type: GrantFiled: October 28, 2014Date of Patent: April 19, 2016Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, STMicroelectronics, Inc.Inventors: Olivier Nier, Denis Rideau, Pierre Morin, Emmanuel Josse
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Patent number: 9305828Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.Type: GrantFiled: October 28, 2014Date of Patent: April 5, 2016Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SASInventors: Denis Rideau, Emmanuel Josse, Olivier Nier
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Publication number: 20150118823Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.Type: ApplicationFiled: October 28, 2014Publication date: April 30, 2015Inventors: Olivier Nier, Denis Rideau, Pierre Morin, Emmanuel Josse
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Publication number: 20150118805Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.Type: ApplicationFiled: October 28, 2014Publication date: April 30, 2015Inventors: Denis Rideau, Elise Baylac, Emmanuel Josse, Pierre Morin, Olivier Nier
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Publication number: 20150118824Abstract: One or more embodiments of the invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a surface of a semiconductor structure having a stressed semiconductor layer and an insulator layer, at least two first trenches in a first direction delimiting a first dimension of at least one first transistor to be formed in the semiconductor structure; performing a first anneal to decrease the viscosity of the insulating layer; and forming, in the surface after the first anneal, at least two second trenches in a second direction delimiting a second dimension of the at least one transistor.Type: ApplicationFiled: October 28, 2014Publication date: April 30, 2015Inventors: Denis Rideau, Emmanuel Josse, Olivier Nier
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Publication number: 20090134441Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.Type: ApplicationFiled: February 4, 2009Publication date: May 28, 2009Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Philippe Candellier, Thierry Devoivre, Emmanuel Josse, Sebastien Lefebvre
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Patent number: 7504683Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer (13) of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.Type: GrantFiled: November 15, 2006Date of Patent: March 17, 2009Assignees: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Philippe Candelier, Thierry Devoivre, Emmanuel Josse, Sébastien Lefebvre
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Publication number: 20070114596Abstract: A non-volatile memory element includes a transistor for selecting the element and a capacitor for recording a binary value by electrical breakdown of an insulating layer (13) of the capacitor. A structure of the memory element is modified in order to allow a higher degree of integration of the element within an electronic circuit of the MOS type. In addition, the memory element is made more robust with respect to a high electrical voltage (VDD) used for recording the binary value. The transistor includes a drain in the substrate with electric field drift in a longitudinal direction extending towards the capacitor. The electric field drift region for the drain includes a first extension underneath the gate of the transistor opposite the source and a second extension underneath the insulating layer of the capacitor. Doping of the substrate for the electric field drift region is limited to a region substantially corresponding to a distance between the gate and an electrode of the capacitor.Type: ApplicationFiled: November 15, 2006Publication date: May 24, 2007Applicants: STMicroelectronics S.A., STMicroelectronics (Crolles 2) SASInventors: Philippe Candelier, Thierry Devoivre, Emmanuel Josse, Sebastien Lefebvre
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Patent number: 7078764Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1,PL2 extending between the source and drain regions, and forming two very fine pillars.Type: GrantFiled: May 24, 2004Date of Patent: July 18, 2006Assignee: STMicroelectronics, S.A.Inventors: Thomas Skotnicki, Emmanuel Josse
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Patent number: 6861684Abstract: The vertical transistor includes, on a semiconductor substrate, a vertical pillar 5 having one of the source and drain regions at the top, the other of the source and drain regions being situated in the substrate at the periphery of the pillar, a gate dielectric layer 7 situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The gate includes a semiconductor block having a first region 800 resting on the gate dielectric layer 7 and a second region 90 facing at least portions of the source and drain regions and separated from those source and drain region portions by dielectric cavities 14S, 14D.Type: GrantFiled: April 2, 2002Date of Patent: March 1, 2005Assignee: STMicroelectronics S.A.Inventors: Thomas Skotnicki, Emmanuel Josse
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Publication number: 20040266112Abstract: The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion 15 resting on the flanks of the pillar and an isolated internal portion 14 situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1, PL2 extending between the source and drain regions, and forming two very fine pillars.Type: ApplicationFiled: May 24, 2004Publication date: December 30, 2004Applicant: STMicroelectronics SAInventors: Thomas Skotnicki, Emmanuel Josse