Patents by Inventor Emmanuelle Merced Grafals

Emmanuelle Merced Grafals has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10354724
    Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 16, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Emmanuelle Merced-Grafals, Juan P. Saenz
  • Publication number: 20190088323
    Abstract: A memory device is provided that includes a memory controller coupled to a memory array. The memory controller is adapted to perform a closed loop training interval and perform an open loop programming interval. The closed loop training interval determines a corresponding first state successful voltage and a corresponding second state successful voltage for a first group of memory cells each including a barrier modulated switching structure. The open loop programming interval programs a second group of memory cells each including a barrier modulated switching structure to a first state and a second state using the corresponding first state successful voltage and the corresponding second state successful voltage, respectively.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 21, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Emmanuelle Merced-Grafals, Juan P. Saenz
  • Publication number: 20190066781
    Abstract: A memory device is provided that includes a memory array having a plurality of reversible resistance-switching memory cells, and a memory controller coupled to the memory array. The memory controller is adapted to program a first reversible resistance-switching memory cell in the memory array to a predetermined data state, determine a program loop count associated with the program step, and retire the first reversible resistance-switching memory cell from further use for host data storage based on the associated program loop count.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Bijesh Rajamohanan, Srinitya Musunuru, Emmanuelle Merced-Grafals
  • Publication number: 20180277208
    Abstract: A memory device is provided that includes a memory controller coupled to a memory cell including a barrier modulated switching structure. The memory controller is adapted to program the memory cell to a first programming state, and program the memory cell to one of a plurality of target programming states from the first programming state.
    Type: Application
    Filed: September 25, 2017
    Publication date: September 27, 2018
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Deepak Kamalanathan, Juan P. Saenz, Tanmay Kumar, Emmanuelle Merced-Grafals, Sebastian J. M. Wicklein
  • Patent number: 9842647
    Abstract: Examples include a method of programming resistive random access memory (RRAM) array for analog computations. In some examples, a selected RRAM cell of the RRAM array may be programmed with a selected target conductance and a programmed conductance error of the selected RRAM cell may be determined. A neighboring RRAM cell may be programmed with an error corrected target conductance that is a function of a neighboring target conductance and the programmed conductance error of the selected RRAM cell. The neighboring RRAM cell may be in a same row or a same column as the selected RRAM cell. The selected RRAM cell and neighboring RRAM cell are programmed such that the RRAM array is programmed for an analog computation.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 12, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: John Paul Strachan, Brent Buchanan, Emmanuelle Merced Grafals