Patents by Inventor Emmanuelle Serret

Emmanuelle Serret has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for decomposing lines of an electronic circuit
    Patent number: 8883625
    Abstract: A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: November 11, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Vincent Farys, Emmanuelle Serret
  • METHOD FOR DECOMPOSING LINES OF AN ELECTRONIC CIRCUIT
    Publication number: 20120241975
    Abstract: A method for defining parallel lines extending along a first direction in a same level of an integrated circuit, among which at least first and second lines separated by an even number of lines are interconnected, a space having a width at least equal to the minimum space between two lines separated by one line being left free, in a second direction perpendicular to the first direction, on either side of a minimum rectangle containing the first and the second lines.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 27, 2012
    Inventors: Vincent Farys, Emmanuelle Serret
  • Manufacture of 3 dimensional MIM capacitors in the last metal level of an integrated circuit
    Patent number: 7796372
    Abstract: A method is for fabricating an integrated circuit formed from a substrate and including several metallic interconnection levels in which, in a same plane parallel to the main plane of the substrate, is a plurality of thick horizontal metallic interconnection lines, as well as one or several MIM capacitors fitted with metallic electrodes that are orthogonal to the main plane of the substrate.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: September 14, 2010
    Assignee: STMicroelectronics SA
    Inventors: Sébastien Cremer, Jean-Christophe Giraudin, Emmanuelle Serret
  • MANUFACTURE OF 3 DIMENSIONAL MIM CAPACITORS IN THE LAST METAL LEVEL OF AN INTEGRATED CIRCUIT
    Publication number: 20080239618
    Abstract: A method is for fabricating an integrated circuit formed from a substrate and including several metallic interconnection levels in which, in a same plane parallel to the main plane of the substrate, is a plurality of thick horizontal metallic interconnection lines, as well as one or several MIM capacitors fitted with metallic electrodes that are orthogonal to the main plane of the substrate.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 2, 2008
    Applicant: STMicroelectronics SA
    Inventors: Sebastien Cremer, Jean-Christophe Giraudin, Emmanuelle Serret