Patents by Inventor Emo Hilbrand Klaassen

Emo Hilbrand Klaassen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6944937
    Abstract: The present invention provides a method of manufacturing a magnetoresistive read head which reduces electrostatic discharge and allows measurement of gap resistances in the head.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: September 20, 2005
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran
  • Publication number: 20040090715
    Abstract: A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together.
    Type: Application
    Filed: June 30, 2003
    Publication date: May 13, 2004
    Applicant: Hitachi Global Storage Technologies
    Inventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran
  • Patent number: 6678127
    Abstract: A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: January 13, 2004
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran
  • Publication number: 20020085318
    Abstract: A first read gap layer has a resistance RG1 between a first shield layer and one of the first and second lead layers of a read head and the second read gap layer has a resistance RG2 between a second shield layer and said one of the first and second lead layers of the read head. A connection is provided via a plurality of resistors between a first node and each of the first and second shield layers wherein the plurality of resistors includes at least first and second resistors RS1 and RS2 and the first node is connected to said one of the first and second lead layers. A second node is located between the first and second resistors RS1 and RS2. An operational amplifier has first and second inputs connected to the first and second nodes respectively so as to be across the first resistor RS1 and has an output connected to the first node for maintaining the first and second nodes at a common voltage potential. In a first embodiment the first and second shield layers are shorted together.
    Type: Application
    Filed: January 2, 2001
    Publication date: July 4, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard Hsiao, James D. Jarratt, Emo Hilbrand Klaassen, Ian Robson McFadyen, Timothy J. Moran