Patents by Inventor Emre Ayranci

Emre Ayranci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210336584
    Abstract: A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.
    Type: Application
    Filed: May 7, 2021
    Publication date: October 28, 2021
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11152907
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: October 19, 2021
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20210143779
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Application
    Filed: November 19, 2020
    Publication date: May 13, 2021
    Inventors: Emre Ayranci, Miles Sanner
  • Patent number: 11005425
    Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: May 11, 2021
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20210135636
    Abstract: A receiver front end (300) having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch (260) is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier.
    Type: Application
    Filed: January 28, 2019
    Publication date: May 6, 2021
    Inventors: Miles SANNER, Emre AYRANCI
  • Patent number: 10951252
    Abstract: Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: March 16, 2021
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10938349
    Abstract: Various methods and circuital arrangements for reducing a turn ON time of a cascode amplifier are presented. According to one aspect, a configurable switching arrangement coupled to a cascode transistor of the amplifier shorts a gate of the cascode transistor to a reference ground during an inactive mode of operation of the amplifier. During an active mode of operation of the amplifier, the configurable switching arrangement couples a gate capacitor to the gate of the cascode transistor that is pre-charged to a voltage that is higher than a gate biasing voltage to the cascode transistor, which ensures that cascode transistor turns ON much quicker than the traditional method of grounding the cap, hence provide a final current flow through the cascode amplifier in a shorter time by not limiting the turn ON time of the input transistor. The gate biasing voltage is coupled to the gate capacitor via a resistor.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: March 2, 2021
    Assignee: PSEMI CORPORATION
    Inventors: Emre Ayranci, Niraja Shreekant Paranjape
  • Publication number: 20210058044
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Application
    Filed: September 2, 2020
    Publication date: February 25, 2021
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10862441
    Abstract: A front end module (FEM) integrated circuit (IC) architecture that uses the same LNA in each of several frequency bands extending over a wide frequency range. In some embodiments, switched impedance circuits distributed throughout the front end circuit allow selection of the frequency response and impedances that are optimized for particular performance parameters targeted for a desired device characteristic. Such switched impedance circuits tune the output and input impedance match and adjust the gain of the LNA for specific operating frequencies and gain targets. In addition, adjustments to the bias of the LNA can be used to optimize performance trade-offs between the total direct current (DC) power dissipated versus radio frequency (RF) performance. By selecting appropriate impedances throughout the circuit using switched impedance circuits, the LNA can be selectively tuned to operate optimally at a selected bias for operation within selected frequency bands.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: December 8, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20200343862
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Application
    Filed: May 13, 2020
    Publication date: October 29, 2020
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Publication number: 20200328724
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 15, 2020
    Inventors: Emre Ayranci, Miles Sanner
  • Publication number: 20200321935
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 8, 2020
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Patent number: 10771025
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Publication number: 20200266778
    Abstract: A receiver topology for supporting various combinations of interband carrier aggregation (CA) signals, intraband non-contiguous CA and non-CA signals having different combinations of signals aggregated therein.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Publication number: 20200220567
    Abstract: Methods and devices addressing design of reconfigurable wideband LNAs to meet stringent gain, noise figure, and linearity requirements with multiple gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements, such as 5G NR radios. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Publication number: 20200220508
    Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10700658
    Abstract: A flexible multi-path RF adaptive tuning network switch architecture that counteracts impedance mismatch conditions arising from various combinations of coupled RF band filters, particularly in a Carrier Aggregation-based (CA) radio system. In one version, a digitally-controlled tunable matching network is coupled to a multi-path RF switch in order to provide adaptive impedance matching for various combinations of RF band filters. Optionally, some or all RF band filters include an associated digitally-controlled filter pre-match network to further improve impedance matching. In a second version, some or all RF band filters coupled to a multi-path RF switch include a digitally-controlled phase matching network to provide necessary per-band impedance matching. Optionally, a digitally-controlled tunable matching network may be included on the common port of the multi-path RF switch to provide additional impedance matching capability.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Ke Li, James Francis McElwee, Tero Tapio Ranta, Kevin Roberts, Chih-Chieh Cheng
  • Patent number: 10700650
    Abstract: Methods and devices addressing design of wideband LNAs with gain modes are disclosed. The disclosed teachings can be used to reconfigure RF receiver front-end to operate in various applications imposing stringent and conflicting requirements. Wideband and narrowband input and output matching with gain modes using a combination of the same hardware and a switching network are also disclosed. The described methods and devices also address carrier aggregation requirements and provide solutions that can be used both in single-mode and split-mode operations.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 30, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner, Phanindra Yerramilli
  • Patent number: 10686409
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 16, 2020
    Assignee: pSemi Corporation
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Patent number: 10673401
    Abstract: An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 2, 2020
    Assignee: pSemi Corporation
    Inventors: Emre Ayranci, Miles Sanner