Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.

Abstract: A method of filtering overlay data by field is provided in the present invention. The method includes the following steps. A minimum number of measure points per field on a semiconductor substrate is decided. Field data filtering rules are set. Overlay raw data is inputted. A raw data filtration is performed to the overlay raw data by field according to the field data filtering rules. Modified exposure parameters are generated for each field according to overlay data of remaining measure points per field after the raw data filtration when the number of the remaining measure points per field is larger than or equal to the minimum number of the measure points per field. Accordingly, the modified exposure parameters will be more effective in reducing the overlay error because more outliers may be filtered out before generating the modified exposure parameters.

Abstract: A semiconductor device includes a semiconductor substrate, semiconductor fins; and a first fin bump between the semiconductor fins. The first fin bump includes a first sidewall spacer. The first sidewall spacer includes a solid-state dopant source layer and an insulating buffer layer.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a dopping layer, and a dielectric layer. The substrate has a plurality of fin portions and at least one recessed portion. The recessed portion is located between the fin portions. The bottom surface of the recessed portion is lower than the surface of the substrate between the fin portions. The dopping layer is disposed on the sidewall of the fin portions, the surface of the substrate, and the sidewall and the bottom portion of the recessed portion. The dielectric layer is disposed on the dopping layer. The top surface of the dopping layer and the top surface of the dielectric layer are lower than the top surface of each of the fin portions.

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction. A total height of the gate isolation structure is greater than a height of the shallow trench isolation structure formed on the semiconductor substrate and located between the fin structures.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a first dielectric layer, a first doping layer of a first conductivity type, and a second doping layer of a second conductivity type. The substrate has a fin portion. The first dielectric layer is disposed on the substrate and surrounds the fin portion. The first doping layer of the first conductivity type is disposed on the first dielectric layer and is located on two opposite sidewalls of the fin portion. The second doping layer of the second conductivity type is disposed on the two opposite sidewalls of the fin portion and is located between the fin portion and the first doping layer. The first doping layer covers a sidewall and a bottom surface of the second doping layer.

Abstract: A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a plurality of fin shaped structures, a trench, a spacing layer and a dummy gate structure. The fin shaped structures are disposed on a substrate. The trench is disposed between the fin shaped structures. The spacing layer is disposed on sidewalls of the trench, wherein the spacing layer has a top surface lower than a top surface of the fin shaped structures. The dummy gate structure is disposed on the fin shaped structures and across the trench.

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.

Abstract: A semiconductor device includes a substrate, a first insulating structure and a gate structure. The substrate includes at least two fin structures protruding from a top surface of the substrate, the substrate includes a first recess and a second recess under the first recess, and the first recess and the second recess are disposed between the fin structures, in which a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure. The first insulating structure fills the second recess. The gate structure is disposed on the first insulating structure, in which the first recess and the second recess are filled up with the gate structure and the first insulating structure.

Abstract: A semiconductor device having metal gate includes a substrate, a metal gate formed on the substrate, a pair of spacers formed on sidewalls of the metal gate, a contact etch stop layer (CESL) covering the spacers, an insulating cap layer formed on the metal gate, the spacers and the CESL, and an ILD layer surrounding the metal gate, the spacers, the CESL and the insulating cap layer. The metal gate, the spacers and the CESL include a first width, and the insulating cap layer includes a second width. The second width is larger than the first width. And a bottom of the insulating cap layer concurrently contacts the metal gate, the spacers, the CESL, and the ILD layer.

Abstract: A FinFET and a method of forming the same are provided. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

Abstract: The present invention provides a method for forming a semiconductor structure, including the following steps: first, a substrate is provided, an interlayer dielectric (ILD) is formed on the substrate, a first dummy gate is formed in the ILD, wherein the first dummy gate includes a dummy gate electrode and two spacers disposed on two sides of the dummy gate electrode respectively. Next, two contact holes are formed in the ILD at two sides of the first dummy gate respectively. Afterwards, the dummy gate electrode is removed, so as to form a gate recess in the ILD, a first material layer is filled in the gate recess and a second material layer is filled in the two contact holes respectively, and an anneal process is performed on the first material layer and the second material layer, to bend the two spacers into two inward curving spacers.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.

Abstract: The present invention provides a semiconductor structure, the semiconductor structure comprises a substrate having a dielectric layer disposed thereon, a gate conductive layer disposed on the substrate and disposed in the dielectric layer, two spacers, disposed on two sides of the gate conductive layer respectively, wherein a top surface of the two spacers is lower than a top surface of the gate conductive layer, and a cap layer overlying the top surface and two sidewalls of the gate conductive layer, wherein parts of the cap layer are located right above the two spacers.

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.

Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.