Patents by Inventor En-Shao Liu
En-Shao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824002Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.Type: GrantFiled: June 28, 2019Date of Patent: November 21, 2023Assignee: Intel CorporationInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Walid M. Hafez, Chia-Hong Jan, Jiansheng Xu
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Patent number: 11114538Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.Type: GrantFiled: December 21, 2018Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
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Patent number: 10923574Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ?-shape, L-shape, or ?-shape, for example.Type: GrantFiled: September 13, 2019Date of Patent: February 16, 2021Assignee: Intel CorporationInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan
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Publication number: 20200411435Abstract: An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: En-Shao LIU, Joodong PARK, Chen-Guan LEE, Walid M. HAFEZ, Chia-Hong JAN, Jiansheng XU
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Patent number: 10535747Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a âTâ shape or various derivatives of that shape such as -shape or -shape, for example.Type: GrantFiled: December 23, 2015Date of Patent: January 14, 2020Assignee: INTEL CORPORATIONInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Chia-Hong Jan
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Publication number: 20200006509Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, C-shape, -shape, ?-shape, L-shape, or ?-shape, for example.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Applicant: INTEL CORPORATIONInventors: EN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, JUI-YEN LIN, CHIA-HONG Jan
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Patent number: 10431661Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or ?-shape, for example.Type: GrantFiled: December 23, 2015Date of Patent: October 1, 2019Assignee: INTEL CORPORATIONInventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan
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Publication number: 20190123164Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Applicant: Intel CorporationInventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
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Patent number: 10204999Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.Type: GrantFiled: July 17, 2015Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
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Publication number: 20180374927Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a âTâ shape or various derivatives of that shape such as -shape or -shape, for example.Type: ApplicationFiled: December 23, 2015Publication date: December 27, 2018Applicant: INTEL CORPORATIONInventors: EN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, CHIA-HONG Jan
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Publication number: 20180350932Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or J-shape, for example.Type: ApplicationFiled: December 23, 2015Publication date: December 6, 2018Applicant: INTEL CORPORATIONInventors: EN-SHAO LIU, JOODONG PARK, CHEN-GUAN LEE, JUI-YEN LIN, CHIA-HONG Jan
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Publication number: 20180197966Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.Type: ApplicationFiled: July 17, 2015Publication date: July 12, 2018Applicant: Intel CorporationInventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan