Abstract: A method includes instantiating a simulation of an electronic design for a device under test (DUT) in hardware design language responsive to a user selection thereof. A subset of leaf nodes from a plurality of leaf nodes from the electronic design with input/output signaling of more than two values is identified. A hierarchical path for each leaf node of the plurality of leaf nodes of the electronic design for the DUT with respect to a testbench is calculated. A bypass module for the subset of leaf nodes is generated. The bypass module is generated in response to detecting presence of the subset of leaf nodes in the electronic design with input/output signaling of more than two values. The bypass module facilitates communication between the testbench and the subset of leaf nodes. Leaf nodes other than the subset of leaf nodes communicate with the testbench without communicating through the bypass module.

Abstract: Effective differential dynamic range in a differential pixel detector is increased by avoiding saturation effects due to common mode contribution in optical energy to be detected. Photocurrent generated by each photodetector pair is directly integrated by an associated capacitor over an integration time T. Within time T, before either integrated capacitor voltage reaches Vsat for the photodetector, at least one of the capacitors is reset to a voltage such that the desired differential detector signal is still determinable. Reset may be generated externally or internally to the differential pixel detector.

Abstract: A disk drive having a motor and a velocity control loop, which includes a frequency detector and a filter. The filter includes a filter section and an accumulator. The filter is programmable in that filter coefficient(s) are dynamically received by the filter section. One embodiment of the filter section is an infinite impulse response filter. One embodiment of the filter is a digital integrated circuit. A method for compensating a control loop by infinite impulse response filtering and accumulating. The control loop may be a position, velocity, acceleration or force control loop. A programmable digital integrated circuit for compensating a velocity control loop having a filter section cascaded with an accumulator. The integrated circuit may include memory for storing filter coefficient(s) for the filter section, thereby not requiring external components.

Abstract: A method and device are disclosed for controlling a polyphase motor having a plurality of windings. The device includes a memory device having stored therein data representing a predetermined driving profile, and driver circuit for driving the windings of the polyphase motor based upon the data provided by the memory unit. A feedback control loop is included having an input connected to a selected winding of the polyphase motor and providing an address signal to the memory device that is based upon a current level of the selected winding at around the time the back electromotive force (bemf) signal corresponding thereto crosses a zero reference, for controlling current provided to the windings by the driver circuit so that, for each winding, the current provided thereto is substantially in phase with a back electromotive force (emf) signal corresponding to the winding.