Patents by Inventor Eng Kian Kenneth Lee
Eng Kian Kenneth Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11087674Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.Type: GrantFiled: February 1, 2018Date of Patent: August 10, 2021Assignees: Nanyang Technological University, Massachusetts Institute of Technology, National University of SingaporeInventors: Joseph Sylvester Chang, Wei Shu, Yong Qu, Eugene A. Fitzgerald, Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Siau Ben Chiah
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Patent number: 10847553Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.Type: GrantFiled: January 12, 2018Date of Patent: November 24, 2020Assignees: Massachusetts Institute of Technology, Nanyang Technological University, National University of SingaporeInventors: Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Eugene A. Fitzgerald, Siau Ben Chiah, Joseph Sylvester Chang, Yong Qu, Wei Shu, Kwang Hong Lee, Bing Wang
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Patent number: 10672608Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.Type: GrantFiled: January 20, 2017Date of Patent: June 2, 2020Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
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Publication number: 20190392755Abstract: Disclosed is a subpixel circuit 310 comprising: a first switching device 311 responsive to a digital periodic signal VP to provide a digital control signal VC relating to a digital data signal VD, the digital periodic signal VP defining 2N+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal VD has a predetermined value at a predetermined one of the 2N+1 time slots; and the subpixel circuit 310 further comprises a second switching device 312 responsive to the control signal Vc to drive an associated light emitting element 320.Type: ApplicationFiled: February 1, 2018Publication date: December 26, 2019Applicants: Nanyang Technological University, Massachusetts Institute of Technology, National University of SingaporeInventors: Joseph Sylvester Chang, Wei Shu, Yong Qu, Eugene A. Fitzgerald, Li Zhang, Eng Kian Kenneth Lee, Soo Jin Chua, Siau Ben Chiah
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Patent number: 10510560Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.Type: GrantFiled: August 31, 2016Date of Patent: December 17, 2019Assignees: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
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Publication number: 20190355766Abstract: A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.Type: ApplicationFiled: January 12, 2018Publication date: November 21, 2019Inventors: Li ZHANG, Eng Kian, Kenneth LEE, Soo Jin CHUA, Eugene A. FITZGERALD, Siau Ben CHIAH, Joseph Sylvester CHANG, Yong QU, Wei SHU, Kwang Hong LEE, Bing WANG
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Patent number: 10324256Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: GrantFiled: December 11, 2017Date of Patent: June 18, 2019Assignees: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Publication number: 20190051516Abstract: A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.Type: ApplicationFiled: January 20, 2017Publication date: February 14, 2019Inventors: Kwang Hong Lee, Li Zhang, Soo Jin Chua, Eng Kian Kenneth Lee, Eugene A. Fitzgerald, Chuan Seng Tan
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Publication number: 20190035628Abstract: Method and structure for reducing substrate fragility. In one embodiment, a substrate for metamorphic epitaxy of a material film is provided, the substrate comprising a passivation layer defining a growth window for the material film on a deposition surface of the substrate, the growth window being laterally spaced from an edge of the substrate.Type: ApplicationFiled: January 19, 2017Publication date: January 31, 2019Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, NATIONAL UNIVERSITY OF SINGAPORE, NANYANG TECHNOLOGICAL UNIVERSITYInventors: Li ZHANG, Kwang Hong LEE, Shuyu BAO, Eng Kian Kenneth LEE, Eugene A. FITZGERALD, Soo Jin CHUA, Chuan Seng TAN
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Publication number: 20180330982Abstract: A method of manufacturing a hybrid substrate is disclosed, which comprises: bonding a first semiconductor substrate to a first combined substrate via at least one layer of dielectric material to form a second combined substrate, the first combined substrate includes a layer of III-V compound semiconductor and a second semiconductor substrate, the layer of III-V compound semiconductor arranged intermediate the layer of dielectric material and second semiconductor substrate; removing the second semiconductor substrate from the second combined substrate to expose at least a portion of the layer of III-V compound semiconductor to obtain a third combined substrate; and annealing the third combined substrate at a temperature about 250° C. to 1000° C. to reduce threading dislocation density of the layer of III-V compound semiconductor to obtain the hybrid substrate.Type: ApplicationFiled: November 10, 2016Publication date: November 15, 2018Applicants: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Shuyu Bao, Eng Kian Kenneth Lee, David Kohen
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Publication number: 20180254197Abstract: A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.Type: ApplicationFiled: August 31, 2016Publication date: September 6, 2018Applicants: Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Kwang Hong Lee, Eng Kian Kenneth Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Viet Cuong Nguyen
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Patent number: 10049947Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.Type: GrantFiled: July 6, 2015Date of Patent: August 14, 2018Assignees: Massachusetts Institute of Technology, Nanyang Technological UniversityInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Eng Kian Kenneth Lee
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Publication number: 20180172903Abstract: A method of forming an integrated circuit is disclosed. The method includes: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: ApplicationFiled: December 11, 2017Publication date: June 21, 2018Applicants: Massachusetts Institute of Technology, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Patent number: 9874689Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: GrantFiled: January 14, 2015Date of Patent: January 23, 2018Assignees: National University of Singapore, Nanyang Technological University, Massachusetts Institute of TechnologyInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee
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Publication number: 20170200648Abstract: A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.Type: ApplicationFiled: July 6, 2015Publication date: July 13, 2017Applicants: Massachusetts Institute of Technology, Nanyang Technological UniversityInventors: Kwang Hong Lee, Chuan Seng Tan, Eugene A. Fitzgerald, Eng Kian Kenneth Lee
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Publication number: 20160327737Abstract: A method (100) of forming an integrated circuit is disclosed. The method comprises: (i) forming at least a pair of optoelectronic devices from at least a first wafer material arranged on a semiconductor substrate, the first wafer material different to silicon; (ii) etching the first wafer material to form a first recess to be filled with a second material; (iii) processing (104) the second material to form a waveguide for coupling the pair of optoelectronic devices to define an optical interconnect; and (iv) bonding (106) at least one partially processed CMOS device layer having at least one transistor to the second semiconductor substrate to form the integrated circuit, the partially processed CMOS device layer arranged adjacent to the optical interconnect. An integrated circuit is also disclosed.Type: ApplicationFiled: January 14, 2015Publication date: November 10, 2016Applicants: MASSACHUSETTS INSTITUTE OF TECHNOLOGY, National University of Singapore, Nanyang Technological UniversityInventors: Wenjia Zhang, Bing Wang, Li Zhang, Zhaomin Zhu, Jurgen Michel, Soo-Jin Chua, Li-Shiuan Peh, Siau Ben Chiah, Eng Kian Kenneth Lee