Patents by Inventor Eng Meow Koon
Eng Meow Koon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8637973Abstract: A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.Type: GrantFiled: March 27, 2007Date of Patent: January 28, 2014Assignee: Micron Technology, Inc.Inventors: Eng Meow Koon, Low Siu Waf, Chan Min Yu, Chia Yong Poo, Ser Bok Leng, Zhou Wei
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Patent number: 8629054Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.Type: GrantFiled: April 6, 2012Date of Patent: January 14, 2014Assignee: Micron Technology, Inc.Inventors: Boon Suan Jeung, Eng Meow Koon, Chia Yong Poo
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Patent number: 8555495Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: November 17, 2011Date of Patent: October 15, 2013Assignee: Micron Technology, Inc.Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Publication number: 20120241957Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.Type: ApplicationFiled: June 8, 2012Publication date: September 27, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Eng Meow Koon, Chia Yong Poo, Boon Suan Jeung
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Publication number: 20120241982Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.Type: ApplicationFiled: April 6, 2012Publication date: September 27, 2012Applicant: Micron Technology, Inc.Inventors: Boon Suan Jeung, Eng Meow Koon, Chia Yong Poo
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Publication number: 20120211896Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.Type: ApplicationFiled: April 30, 2012Publication date: August 23, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Boon Suan Jeung, Chia Yong Poo, Eng Meow Koon
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Patent number: 8168476Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.Type: GrantFiled: September 3, 2010Date of Patent: May 1, 2012Assignee: Micron Technology, Inc.Inventors: Boon Suan Jeung, Chia Yong Poo, Eng Meow Koon
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Patent number: 8138617Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.Type: GrantFiled: August 30, 2004Date of Patent: March 20, 2012Assignee: Round Rock Research, LLCInventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Eng Meow Koon, Ser Bok Leng, Chua Swee Kwang, So Chee Chung, Ho Kwok Seng
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Publication number: 20120064697Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: ApplicationFiled: November 17, 2011Publication date: March 15, 2012Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Patent number: 8115306Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.Type: GrantFiled: February 12, 2010Date of Patent: February 14, 2012Assignee: Round Rock Research, LLCInventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Lou, Eng Meow Koon, Ser Bok Leng, Chun Swee Kwang, So Chee Chung, Ho Kwok Song
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Patent number: 8065792Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: February 15, 2010Date of Patent: November 29, 2011Assignee: Micron Technology, Inc.Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Patent number: 8008126Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.Type: GrantFiled: November 24, 2009Date of Patent: August 30, 2011Assignee: Micron Technology, Inc.Inventors: Boon Suan Jeung, Chia Yong Poo, Low Siu Waf, Eng Meow Koon, Chua Swee Kwang, Huang Shuang Wu, Neo Yong Loo, Zhou Wei
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Patent number: 7947529Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.Type: GrantFiled: October 24, 2007Date of Patent: May 24, 2011Assignee: Micron Technology, Inc.Inventors: Eng Meow Koon, Chia Yong Poo, Boon Suan Jeung, Tay Wuu Yean
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Publication number: 20110084402Abstract: Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites.Type: ApplicationFiled: December 20, 2010Publication date: April 14, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Boon Suan Jeung, Eng Meow Koon, Chia Yong Poo
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Publication number: 20110068454Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.Type: ApplicationFiled: November 29, 2010Publication date: March 24, 2011Applicant: MICRON TECHNOLOGY, INC.Inventors: Eng Meow Koon, Chia Yong Poo, Boon Suan Jeung
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Publication number: 20100330749Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.Type: ApplicationFiled: September 3, 2010Publication date: December 30, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Boon Suan Jeung, Chia Yong Poo, Eng Meow Koon
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Publication number: 20100146780Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: ApplicationFiled: February 15, 2010Publication date: June 17, 2010Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Publication number: 20100140794Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.Type: ApplicationFiled: February 12, 2010Publication date: June 10, 2010Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Lou, Eng Meow Koon, Ser Bok Leng, Chun Swee Kwang, So Chee Chung, Ho Kwok Song
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Patent number: 7712211Abstract: A method for packaging integrated circuit chips (die) is described that includes providing a base substrate with package level contacts, coating a base substrate with adhesive, placing dies on the adhesive, electrically connecting the die to the package level contacts, and removing the backside of the base substrate to expose the backside of the package level contacts. Accordingly, an essentially true chip scale package is formed. Multi-chip modules are formed by filling gaps between the chips with an encapsulant. In an embodiment, chips are interconnected by electrical connections between package level contacts in the base substrate. In an embodiment, substrates each having chips are adhered back-to-back with through vias formed in aligned saw streets to interconnect the back-to-back chip assembly.Type: GrantFiled: December 23, 2003Date of Patent: May 11, 2010Assignee: Micron Technology, Inc.Inventors: Yong Poo Chia, Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua
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Publication number: 20100068851Abstract: Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.Type: ApplicationFiled: November 24, 2009Publication date: March 18, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Boon Suan Jeung, Chia Yong Poo, Low Siu Waf, Eng Meow Koon, Chua Swee Kwang, Huang Shuang Wu, Neo Yong Loo, Zhou Wei