Abstract: A method and apparatus is described for assigning columns of an LDPC H matrix to a plurality of decoding logics for efficient decoding of codewords. The rows of the LDPC H matrix are evaluated in a number of different orderings, and for each row in each ordering, a number of columns containing non-zero circulants are determined that cannot be evenly distributed to a plurality of decoding logics. As each row is evaluated, one or more columns of the LDPC H matrix are assigned to temporary bins for storage. After the LDPC H matrix has been evaluated a plurality of times, the arrangement that resulted in the fewest number of “mismatched” columns is selected, and the columns of the LDPC H matrix that were assigned to the temporary storage bins for that particular row arrangement is used to assign the columns in the bins to the plurality of decoding logics.

Abstract: A method and apparatus for efficient data decoding is described. Data is encoded by an LDPC encoder using a G matrix. An LDPC decoder uses a modified H matrix to decode encoded blocks of data, the modified H matrix having at least two columns of its circulants swapped with each other. The encoded blocks of data are stored, decoded and reconstructed in an order that considers the circulants in the columns that have been swapped.

Abstract: Look-ahead LDPC decoder. In an exemplary embodiment, a method includes generating a message (QA) to a first check node, the QA message is generated from a result (RA) from the first check node, and generating a message (QB) to a second check node, the QB message is generated from the result (RA) and is transmitted to avoid decoder stall. The method also includes receiving a result (R?A) from the first check node, computing a difference (R?A) between the result (R?A) and the result (RA), and receiving a result (R?B) from the second check node. The method also includes computing a bit value P(B) using the difference (R?A) and the result (R?B).

Abstract: Methods and systems are disclosed for decoding codewords, wherein codewords comprise at least one circulant and are stored in a first dimension of a matrix, and wherein each circulant in a codeword is associated with a location in a second dimension in the matrix. The method includes determining whether a first location in a second dimension of a first circulant of a first codeword corresponds to a second location in the second dimension of a second circulant of a second codeword. The method includes, in response to determining that the first location does not correspond to the second location, decoding the first and second circulant with a first decoding process. The method includes, in response to determining that the first location corresponds to the second location, decoding the first and second circulant with a second decoding process.

Abstract: There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.

Abstract: There is provided, in accordance with an embodiment, a method of decoding codewords in conjunction with a low-density parity-check (LDPC) code that defines variable nodes and check nodes, the method comprising receiving a codeword over a data channel; evaluating quality of the data channel; and iteratively updating values of the variable nodes to decode the codeword; wherein the values of the variable nodes are updated at different levels of numeric precision depending on the evaluated quality of the data channel.

Abstract: Disclosed herein are systems and methods for a signed-magnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's complement based adder includes circuitry for converting operands from their signed-magnitude representations to their one's complement representations, circuitry for adding operands in their one's complement representations, and circuitry for converting the resulting sum into a signed-magnitude format.

Abstract: Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to decode codewords and decoder firmware configured to control one or more decoding parameters of the decoder. The decoder includes a recovery unit configured to store recovery instructions. The decoder is further configured to execute the stored recovery instructions without interaction with the decoder firmware when the decoding fails.

Abstract: The present disclosure includes systems and methods for acquiring a first set of information for a plurality of low density parity check (LDPC)-encoded data symbols, acquiring a second set of information for the plurality of LDPC-encoded data symbols, and selecting a window including a subset of the plurality of LDPC-encoded data symbols. The present disclosure includes acquiring a decoder schedule having information for controlling the decoder, wherein the information in the decoder schedule includes decoding instructions based on a configuration of at least one of the first set of information and the second set of information. The present disclosure further includes determining a likelihood of an error in the window using the decoding instructions in the decoder schedule, and updating the second set of information for selected data symbols of the subset based on the likelihood of an error in the window.

Abstract: A group of numbers from which the smallest and second-smallest are to be selected are compared in a cascaded tree. Each comparison stage will select the smallest number from two numbers output by the previous stage, into which four numbers are input. The second-smallest number is one of the other three inputs to the previous stage and, as before, all bits of the second-smallest number will not be known until the smallest number is determined. However, because at each stage of the determination, the next stage is reached because the bit values being examined are the same, those bit values of the second-smallest number (and indeed of the smallest number) are known ahead of the final determination of the smallest number. Accordingly, one can begin to output bits of the second-smallest number (as well as of the smallest number) even before that final determination.

Abstract: Systems, methods, and other embodiments associated with iterative decoders are described. According to one embodiment, an apparatus includes a set of decoders that are configured to receive data to be decoded. The apparatus may also include a controller configured to separately control each decoder to initiate a decoding sequence based on an occurrence of a transition point. The transition point is a global transition that occurs iteratively for the set of decoders and is based on iterations in a decoding sequence.

Abstract: The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes R banks; Q banks; circuitry configured to store R data for a current codeword in a first R bank of the R banks and store R data for a previous codeword in a second R bank of the R banks; circuitry configured to alternate among the R banks for storing current codeword R data; circuitry configured to store Q data for the current codeword in a first Q bank of the Q banks and store Q data for the previous codeword in a second Q bank of the Q banks; and circuitry configured to alternate among the Q banks for storing current codeword Q data. The apparatus can include circuitry configured to interleave read accesses among the R banks.

Abstract: A decoder for a communication system includes a channel detection module configured to receive initial estimates of respective code words, wherein the initial estimates of the respective code words correspond to a signal received via a communication channel, arrange the initial estimates of the respective code words into a plurality of groups, and generate probability information associated with selected data bits of the respective code words in the plurality of groups, wherein the probability information indicates probabilities of decoding decisions of the selected data bits. A computation module is configured to generate bit estimations for each of the selected data bits based on the probability information and feedback information. A decoding module is configured to selectively generate, the feedback information and an estimate signal corresponding to the respective code words.

Abstract: Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme.

Abstract: Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to decode codewords and decoder firmware configured to control one or more decoding parameters of the decoder. The decoder includes a recovery unit configured to store recovery instructions. The decoder is further configured to execute the stored recovery instructions without interaction with the decoder firmware when the decoding fails.

Abstract: Disclosed herein are systems and methods for a signed-magnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's complement based adder includes circuitry for converting operands from their signed-magnitude representations to their one's complement representations, circuitry for adding operands in their one's complement representations, and circuitry for converting the resulting sum into a signed-magnitude format.

Abstract: Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to perform a decoding process on codewords to verify that the codewords meet coding constraints. The decoder includes a recovery unit configured to store recovery instructions for performing a modified decoding process. The recovery unit is further configured to execute the stored recovery instructions when a decoded codeword fails to meet the coding constraints.

Abstract: Systems and methods for acquiring a first set of information for a plurality of low density parity check (LDPC)-encoded data symbols, acquiring a second set of information for the plurality of LDPC-encoded data symbols, and selecting a window including a subset of the plurality of LDPC-encoded data symbols. The systems and methods include acquiring a decoder schedule having information for controlling the decoder, wherein the information in the decoder schedule includes decoding instructions based on a configuration of at least one of the first set of information and the second set of information. The systems and methods further include determining a likelihood of an error in the window using the decoding instructions in the decoder schedule, and updating the second set of information for selected data symbols of the subset based on the likelihood of an error in the window.

Abstract: Encoder and decoder apparatus and methods derive a plurality of parity bits from a single codeword. Encoder apparatus may include a receive module receiving a data stream, a parity generation module generating a plurality of parity bits based on the data stream and a word of a tensor-product code, and a parity insertion module combining the plurality of parity bits and the data stream to generate encoded bits. Decoder apparatus may include a detector receiving and outputting encoded data, a first decoder generating first log-likelihood ratios (LLRs) from the encoded data, an error recovery module generating second LLRs from the encoded data, a second decoder that derives syndrome data from the first and second LLRs, a post-processor that combines data from the first decoder with error events from the error recovery module to generate corrected data, the post-processor further identifying a plurality of parity bits in the corrected data.

Abstract: A communication system includes an encoder configured to encode first data words to generate code words. A modulator is configured to modulate the code words into a first signal that is transmitted on a communication channel. A demodulator is configured to demodulate a second signal, received from the communication channel, into estimates of the code words. The second signal is based on the first signal. A decoding module is configured to group the estimates of the code words into a plurality of groups of correlated data bits, wherein the correlated data bits include statistical relationships between different data bits, generate a plurality of group estimate signals each corresponding to a respective one of the plurality of groups of correlated data bits, and generate, by combining the plurality of group estimate signals, an estimate signal corresponding to the first data words.