Patents by Inventor Enisa Harris

Enisa Harris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multi-chip package with partial integrated heat spreader
    Patent number: 11004768
    Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Muhammad S. Islam, Enisa Harris, Suzana Prstic, Sergio Chan Arguedas, Sachin Deshmukh, Aravindha Antoniswamy, Elah Bozorg-Grayeli
  • MULTI-CHIP PACKAGE WITH PARTIAL INTEGRATED HEAT SPREADER
    Publication number: 20210035886
    Abstract: A multi-chip package includes multiple IC die interconnected to a package substrate. An integrated heat spreader (IHS) is located over one or more primary IC die, but is absent from over one or more secondary IC die. Thermal cross-talk between IC dies and/or thermal performance of individual IC dies may be improved by constraining the dimensions of the IHS to be over less than all IC die of the package. A first thermal interface material (TIM) may be between the IHS and the primary IC die, but absent from over the secondary IC die. A second TIM may be between a heat sink and the IHS and also between the heat sink and the secondary IC die. The heat sink may be segmented, or have a non-planarity to accommodate differences in z-height across the IC die and/or as a result of constraining the dimensions of the IHS to be over less than all IC die.
    Type: Application
    Filed: August 1, 2019
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Muhammad S. Islam, Enisa Harris, Suzana Prstic, Sergio Chan Arguedas, Sachin Deshmukh, Aravindha Antoniswamy, Elah Bozorg-Grayeli