Patents by Inventor Enrico Varesi
Enrico Varesi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190324671Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: ApplicationFiled: April 2, 2019Publication date: October 24, 2019Applicant: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
-
Patent number: 10439000Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.Type: GrantFiled: November 8, 2018Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventors: Paolo Fantini, F. Daniel Gealy, Enrico Varesi, Swapnil A. Lengade
-
Publication number: 20190115532Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A component of a memory cell, such as a selector device, storage device, or self-selecting memory device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. The chalcogenide material, for instance, may have a composition of selenium, germanium, and at least one of boron, aluminum, gallium, indium, or thallium. The chalcogenide material may in some cases also include arsenic, but may in some cases lack arsenic.Type: ApplicationFiled: December 20, 2018Publication date: April 18, 2019Inventors: Enrico Varesi, Paolo Fantini, Lorenzo Fratin, Swapnil A. Lengade
-
Publication number: 20190102099Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: INTEL CORPORATIONInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
-
Patent number: 10248351Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: GrantFiled: September 29, 2017Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
-
Publication number: 20190081103Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.Type: ApplicationFiled: November 8, 2018Publication date: March 14, 2019Inventors: Paolo Fantini, F. Daniel Gealy, Enrico Varesi, Swapnil A. Lengade
-
Publication number: 20190044060Abstract: A phase change memory (PCM) cell can include a PCM layer. A first electrode and a second electrode disposed on opposite sides of the PCM layer. The first electrode, the second electrode, or both includes a metal ceramic composite material layer disposed between an upper barrier layer and a lower barrier layer and wherein the metal ceramic composite material layer provides a corresponding electrode with an electrical resistivity of from 10 mOhm-cm to 1000 mOhm-cm.Type: ApplicationFiled: June 4, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Stephen W. Russell, Andrea Gotti, Andrea Redaelli, Enrico Varesi, Innocenzo Tortorelli, Lorenzo Fratin, Alessandro Sebastiani
-
Publication number: 20190019947Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.Type: ApplicationFiled: September 4, 2018Publication date: January 17, 2019Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
-
Patent number: 10163977Abstract: Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.Type: GrantFiled: March 22, 2017Date of Patent: December 25, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Paolo Fantini, F. Daniel Gealy, Enrico Varesi, Swapnil A. Lengade
-
Patent number: 10153428Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.Type: GrantFiled: March 29, 2017Date of Patent: December 11, 2018Assignee: MICRON TECHNOLOGY, INC.Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
-
Publication number: 20180114902Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.Type: ApplicationFiled: December 14, 2017Publication date: April 26, 2018Inventors: Andrea Redaelli, Mattia Boniardi, Enrico Varesi, Raffaella Calarco, Jos E. Boschker
-
Publication number: 20180033962Abstract: The present disclosure includes textured memory cell structures and method of forming the same. In one or more embodiments, a memory cell includes a buffer portion formed on an amorphous portion and an active portion formed on the buffer portion, wherein the active portion is textured with a single out of plane orientation.Type: ApplicationFiled: July 29, 2016Publication date: February 1, 2018Inventors: Andrea Redaelli, Mattia Boniardi, Enrico Varesi, Raffaella Calarco, Jos E. Boschker
-
Publication number: 20170271582Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.Type: ApplicationFiled: March 29, 2017Publication date: September 21, 2017Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
-
Patent number: 9634245Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.Type: GrantFiled: January 9, 2015Date of Patent: April 25, 2017Assignee: MICRON TECHNOLOGY, INC.Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
-
Publication number: 20160211017Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely. As a result, current density may be increased at this location, producing heating.Type: ApplicationFiled: March 29, 2016Publication date: July 21, 2016Applicant: MICRON TECHNOLOGY, INC.Inventors: Guy C. Wicker, Fabio Pellizzer, Enrico Varesi, Agostino Pirovano
-
Publication number: 20160204343Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.Type: ApplicationFiled: January 9, 2015Publication date: July 14, 2016Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
-
Patent number: 9343676Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely. As a result, current density may be increased at this location, producing heating.Type: GrantFiled: January 29, 2014Date of Patent: May 17, 2016Assignee: Micron Technology, Inc.Inventors: Guy C. Wicker, Fabio Pellizzer, Enrico Varesi, Agostino Pirovano
-
Publication number: 20140147965Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely. As a result, current density may be increased at this location, producing heating.Type: ApplicationFiled: January 29, 2014Publication date: May 29, 2014Applicant: Micron Technology, Inc.Inventors: Guy C. Wicker, Fabio Pellizzer, Enrico Varesi, Agostino Pirovano
-
Patent number: 8680499Abstract: Some embodiments include memory cells which contain chalcogenide material having germanium in combination with one or both of antimony and tellurium. An atomic percentage of the germanium within the chalcogenide material is greater than 50%; and may be, for example, within a range of from greater than or equal to about 52% to less than or equal to about 78%. In some embodiments, the memory cell has a top electrode over the chalcogenide material, a heater element under and directly against the chalcogenide material, and a bottom electrode beneath the heater element. The heater element may be L-shaped, with the L-shape having a vertical pillar region joining with a horizontal leg region. A bottom surface of the horizontal leg region may be directly against the bottom electrode, and a top surface of the vertical pillar region may be directly against the chalcogenide material.Type: GrantFiled: January 23, 2012Date of Patent: March 25, 2014Assignee: Micron Technology, Inc.Inventors: Davide Erbetta, Luca Fumagalli, Innocenzo Tortorelli, Enrico Varesi
-
Patent number: 8653495Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely.Type: GrantFiled: April 11, 2005Date of Patent: February 18, 2014Assignee: Micron Technology, Inc.Inventors: Guy C. Wicker, Fabio Pellizzer, Enrico Varesi, Agostino Pirovano