Abstract: An IP address assignment method including assigning a chassis serial number to a node during manufacture, generating an array of unique IP addresses composed using the chassis serial number, and assigning a unique IP address from the array to each interface associated with the node.

Abstract: An IP address assignment method including assigning a chassis serial number to a node during manufacture, generating an array of unique IP addresses composed using the chassis serial number, and assigning a unique IP address from the array to each interface associated with the node.

Abstract: Modems at ends of a transmission line are synchronized with each other by a training procedure which initiates each of a plurality of communication sessions occurring while a connection between the modems is established. The initial communication session begins with a long training sequence. Ensuing communication sessions utilize a time-saving short training sequence which includes the following. A coarse timing algorithm establishes synchronization on a symbol boundary from two alternating elements transmitted in accordance with a standard and of which a plurality of amplitude samples are taken. A fine timing algorithm then quickly finds the peak point of the symbol so that the sampling instance can be adjusted accordingly. This is accomplished by identifying, which sample of an element represents the maximum amplitude between the elements. A comparison is made between the identified sample and its preceding one for that element, and the identified sample and its succeeding one for that element.

Abstract: The present invention provides methods and apparatus for synchronous detection of a Frequency Shift Keying (FSK) signal. The demodulation of the FSK signal is performed in the "complex plane" after multiplying the input samples by an unlocked complex carrier in a complex down converter. Two decision bits are generated per real bit. Once bit should be the real decision; the other bit is a "transition" bit between two Bauds. To generate this situation, the last three decisions are considered. If a transition from 0 to 1, or vice-versa, occurs between the first and third bit, then the middle (second) bit should have equal probability to be 0 or 1. If it is 1, timing correction, by moving the sampling window, is done towards the 0 bit. If it is a 0, the sampling window is moved toward the 1 bit. The timing decision is efficiently implemented by taking the three bits as an index to an 8-entry look-up table that generates ADVANCE, DELAY or NO.sub.--OP directions.