Patents by Inventor Erez Amit
Erez Amit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11269799Abstract: A cluster of processing elements has a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking an outcome of a primary processing workload performed by a corresponding primary processing element. A shared cache is provided, having a predetermined cache capacity accessible to each of the processing elements when in the split mode. In the lock mode, the predetermined cache capacity of the shared cache is fully accessible to the at least one primary processing element.Type: GrantFiled: May 3, 2019Date of Patent: March 8, 2022Assignee: Arm LimitedInventors: R Frank O'Bleness, Erez Amit
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Publication number: 20200348985Abstract: A cluster of processing elements has a split mode in which the processing elements are configured to process independent processing workloads, and a lock mode in which the processing elements comprise at least one primary processing element and at least one redundant processing element, each redundant processing element configured to perform a redundant processing workload for checking an outcome of a primary processing workload performed by a corresponding primary processing element. A shared cache is provided, having a predetermined cache capacity accessible to each of the processing elements when in the split mode. In the lock mode, the predetermined cache capacity of the shared cache is fully accessible to the at least one primary processing element.Type: ApplicationFiled: May 3, 2019Publication date: November 5, 2020Inventors: R Frank O'BLENESS, Erez AMIT
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Patent number: 10230542Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: GrantFiled: March 8, 2017Date of Patent: March 12, 2019Assignee: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
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Publication number: 20170180156Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: March 8, 2017Publication date: June 22, 2017Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
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Patent number: 9521011Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: GrantFiled: January 22, 2014Date of Patent: December 13, 2016Assignee: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Moshe Raz, Amit Shmilovich
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Patent number: 9454480Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: GrantFiled: January 22, 2014Date of Patent: September 27, 2016Assignee: Marvell World Trade Ltd.Inventors: Eitan Joshua, Erez Amit, Shaul Chapman, Sujat Jamil, Frank O'Bleness
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Patent number: 9338530Abstract: Methods and systems for implementing versatile optical terminals that detect optical transmission protocols and subsequently adapt to the correct protocol are disclosed. In an embodiment, an interface device for providing an interface for a first network with a passive optical network (PON) is disclosed. The interface device includes a protocol detection circuit for determining whether optical communication signals received from the PON conform to a first optical communication protocol, and a switchover control circuit that reconfigures the interface device to work with a second optical communication protocol when the received optical communication signals do not conform to the first optical communication protocol.Type: GrantFiled: January 22, 2014Date of Patent: May 10, 2016Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Erez Izenberg, Oren Ben-Hayune, Erez Amit, Dimitry Melts, Arie Elias
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Patent number: 8924810Abstract: A data unit is received, wherein the data unit includes a primary information data structure and a primary redundancy data structure. A secondary error correction operation is performed on one or more selected fields within the primary information data structure. After performing the secondary error correction operation, a primary error correction operation is performed on the data unit using the primary redundancy data structure, the primary error correction operation separate from the secondary error correction operation.Type: GrantFiled: December 16, 2013Date of Patent: December 30, 2014Inventors: Erez Izenberg, Oren Shafrir, Erez Amit, Dimitry Melts
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Publication number: 20140201444Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Moshe Raz, Amit Shmilovich
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Publication number: 20140201443Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Moshe Raz, Husam Khshaiboun
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Publication number: 20140201472Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Amit Shmilovich, Moshe Raz, Shaul Chapman, Erez Amit
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Publication number: 20140201326Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 15, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Shaul Chapman, Erez Amit, Noam Mizrahi, Moshe Raz, Husam Khshaiboun, Amit Shmilovich, Sujat Jamil, Frank O'Bleness
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Publication number: 20140201445Abstract: In various embodiments, the present disclosure provides a system comprising a first plurality of processing cores, ones of the first plurality of processing cores coupled to a respective core interface module among a first plurality of core interface modules, the first plurality of core interface modules configured to be coupled to form in a first ring network of processing cores; a second plurality of processing cores, ones of the second plurality of processing cores coupled to a respective core interface module among a second plurality of core interface modules, the second plurality of core interface modules configured to be coupled to form a second ring network of processing cores; a first global interface module to form an interface between the first ring network and a third ring network; and a second global interface module to form an interface between the second ring network and the third ring network.Type: ApplicationFiled: January 22, 2014Publication date: July 17, 2014Applicant: Marvell World Trade Ltd.Inventors: Eitan Joshua, Erez Amit, Shaul Chapman, Sujat Jamil, Frank O'Bleness
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Publication number: 20140133854Abstract: Methods and systems for implementing versatile optical terminals that detect optical transmission protocols and subsequently adapt to the correct protocol are disclosed. In an embodiment, an interface device for providing an interface for a first network with a passive optical network (PON) is disclosed. The interface device includes a protocol detection circuit for determining whether optical communication signals received from the PON conform to a first optical communication protocol, and a switchover control circuit that reconfigures the interface device to work with a second optical communication protocol when the received optical communication signals do not conform to the first optical communication protocol.Type: ApplicationFiled: January 22, 2014Publication date: May 15, 2014Applicant: Marvell International Ltd.Inventors: Erez IZENBERG, Oren BEN-HAYUNE, Erez AMIT, Dimitry MELTS, Arie ELIAS
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Patent number: 8693868Abstract: Methods and systems for implementing versatile optical terminals that detect optical transmission protocols and subsequently adapt to the correct protocol are disclosed. In an embodiment, an interface device for providing an interface for a first network with a passive optical network (PON) is disclosed. The interface device includes a protocol detection circuit for determining whether optical communication signals received from the PON conform to a first optical communication protocol, and a switchover control circuit that reconfigures the interface device to work with a second optical communication protocol when the received optical communication signals do not conform to the first optical communication protocol.Type: GrantFiled: March 14, 2011Date of Patent: April 8, 2014Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Erez Izenberg, Oren Ben-Hayune, Erez Amit, Dimitry Melts, Arie Elias
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Patent number: 8612822Abstract: A data unit is received, wherein the data unit includes a primary information data structure and a primary redundancy data structure. A field in the primary information data structure is detected. A secondary error correction operation is performed on the detected field. After performing the secondary error correction operation, a primary error correction operation is performed on the data unit using the primary redundancy data structure.Type: GrantFiled: January 6, 2011Date of Patent: December 17, 2013Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Erez Izenberg, Oren Shafrir, Erez Amit, Dimitry Melts
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Patent number: 8588242Abstract: Some of the embodiments of the present disclosure provide a method for scheduling processing of packets received from a network, comprising assigning a corresponding queue weight to each of a plurality of queues that are configured to enqueue the packets for processing; for each of the plurality of queues, determining a corresponding multiplication factor (MF) as a function of a number of cycles until a next packet is available from the corresponding queue for processing; and incrementing a plurality of counters, associated with the corresponding plurality of queues, based at least in part on the multiplication factors. Other embodiments are also described and claimed.Type: GrantFiled: January 4, 2011Date of Patent: November 19, 2013Assignee: Marvell Israel (M.I.S.L) Ltd.Inventors: Erez Izenberg, Ruven Torok, Erez Amit, Dimitry Melts
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Patent number: 8522116Abstract: In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit.Type: GrantFiled: July 27, 2011Date of Patent: August 27, 2013Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Oren Shafrir, Erez Izenberg, Erez Amit, Dimitry Melts
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Patent number: 8417982Abstract: Some of the embodiments of the present disclosure provide a method for operating a first in first out (FIFO) memory system in different clock domains, the method comprising receiving a write request in a first clock domain; generating, by a write shift and truncation module in response to receiving the write request, a shifted series of binary numbers such that the shifted series of binary numbers is a reduced sub-set of a first series of binary numbers; and generating, by a binary to Gray conversion module, a series of Gray code numbers corresponding to the shifted series of binary numbers. Other embodiments are also described and claimed.Type: GrantFiled: August 5, 2010Date of Patent: April 9, 2013Assignee: Marvell Israel (M.I.S.L.) Ltd.Inventors: Erez Amit, Dimitry Melts, Erez Izenberg
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Publication number: 20120036415Abstract: In accordance with the teachings described herein, systems and methods are provided for performing forward error correction. A decoder for performing forward error correction for a frame in a data stream includes a state machine configured to determine if a code block within the frame received by the decoder is a complete code block or a partial code block, the frame including a plurality of code blocks. A decoding unit is configured to receive the code block, and, when the code block is a partial code block, to generate an output based on decoding the partial code block and an additional partial decoding result that is input to the decoding unit.Type: ApplicationFiled: July 27, 2011Publication date: February 9, 2012Inventors: Oren Shafrir, Erez Izenberg, Erez Amit, Dimitry Melts