Abstract: An automatic critique of resumes, cover-letters, and/or other types of documents is provided. The invention employs an input document, a processing device, and a set of rules specific to the document type. The processing device searches the document for specific patterns described by the rules, generates a list of potential errors in the document, generates advice on how to correct the errors and may produce various figures of merit for the document.

Abstract: An automatic critique of resumes, cover-letters, and/or other types of documents is provided. The invention employs an input document, a processing device, and a set of rules specific to the document type. The processing device searches the document for specific patterns described by the rules, generates a list of potential errors in the document, generates advice on how to correct the errors and may produce various figures of merit for the document.

Abstract: An automatic critique of resumes, cover-letters, and/or other types of documents is provided. The invention employs an input document, a processing device, and a set of rules specific to the document type. The processing device searches the document for specific patterns described by the rules, generates a list of potential errors in the document, generates advice on how to correct the errors and may produce various figures of merit for the document.

Abstract: A memory controller apparatus for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller apparatus interfaces the microprocessor and the plurality of devices. The microprocessor functions asynchronously with the plurality of devices. The memory controller apparatus comprises a delay line circuitry coupled to receive a selected request for accessing the memory array from one of the microprocessor and the plurality of devices, the delay line means further including means for generating a plurality of memory timing control signals. The memory timing control signals are used for accessing the memory array. The delay line circuitry functions independently of any clock signal. The delay line circuitry is only triggered by the selected request. The memory controller apparatus further comprises a memory state circuitry coupled to the delay line circuitry for controlling sequence and timing of the memory timing control signals.

Abstract: A means and a method of interfacing a memory controller with a high speed synchronous CPU wherein the CPU clock is independent of the memory controller clock. The CPU clock is connected to both the CPU and a control interface state tracker located externally to the memory controller. The control interface state tracker is then connected to the memory controller. A separate clock independent from the one used with the CPU is coupled to the memory controller and drives the operation of the memory controller. During the operation of the computer system, the CPU makes read or write cycle requests of the memory controller. Such cycles are initiated when the CPU sends a cycle "start" indicator to the state tracker. In response, the state tracker activates a start strobe to the memory controller to start the actual memory cycle. The memory controller receives the CPU address and cycle status and determines the page hit/miss condition of the memory access.