Abstract: An imaging system including column-parallel ADCs that operate in response to a single slope global ramp signal and a matched global ramp line signal that has a voltage representative of a dark pixel value. The signal paths of the global ramp signal and the matched global ramp line signal are matched to minimize noise effects. Prior to performing a pixel read operation, the global ramp signal is increased through a first voltage range (below the dark pixel value) to ensure that the column-parallel ADCs are operating in a linear range. The first voltage range can be adjusted to cancel offset error associated with the column parallel ADCs. The column-parallel ADCs provide output signals having a full voltage swing between VDD and ground.

Abstract: A single-poly electrically erasable/programmable CMOS logic memory cell for mobile applications includes a CMOS inverter that share a single polysilicon floating gate, and an enhanced control capacitor including a control gate capacitor and an optional isolated P-well (IPW) capacitor formed below the control gate capacitor. The control gate capacitor includes a polysilicon control gate that is interdigitated with the floating gate and serves as a capacitor plate to induce Fowler-Nordheim (F-N) injection or Band-to-Band Tunneling (BBT) to both program and erase the floating gate. The IPW capacitor is provided in the otherwise unused space below the control gate capacitor by a IPW that is separated from the control/floating gates by a dielectric layer and is electrically connected to the control gate. Both F-N injection and BBT program/erase are performed at 5V or less.

Abstract: An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are read using conventional supply voltages, thereby minimizing power consumption during a read operation. The ultra-low power NVM module of the present invention can be fabricated using conventional VLSI process steps. The ultra-low power NVM module of the present invention also allows simple operation in all modes (i.e., program, erase, read and standby).

Abstract: Near-ground sensing of non-volatile memory (NVM) cells is performed on a selected NVM cell by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and passing the resulting cell current to an integrator, which generates a corresponding sense voltage. The amount of cell current (and resulting sense voltage) is controlled by the programmed/erased state of the NVM cell. The sense voltage is compared with a reference voltage to determine the cell's programmed/erased state. Current through neighbor cells is redirected to the sensing circuit using a special Y decoder to minimize the neighbor effect.

Abstract: An improved ultra-low power NVM module, which exhibits low power consumption and reduced layout area. An array of compact flash memory cells are programmed and erased in response to positive and negative boosted voltages. However, the compact flash memory cells are read using conventional supply voltages, thereby minimizing power consumption during a read operation. The ultra-low power NVM module of the present invention can be fabricated using conventional VLSI process steps. The ultra-low power NVM module of the present invention also allows simple operation in all modes (i.e., program, erase, read and standby).

Abstract: Near-ground sensing of non-volatile memory (NVM) cells is performed on a selected NVM cell by applying a potential to a first terminal, coupling a second terminal to ground, and then decoupling the second terminal and passing the resulting cell current to an integrator, which generates a corresponding sense voltage. The amount of cell current (and resulting sense voltage) is controlled by the programmed/erased state of the NVM cell. The sense voltage is compared with a reference voltage to determine the cell's programmed/erased state. Current through neighbor cells is redirected to the sensing circuit using a special Y decoder to minimize the neighbor effect.

Abstract: A voltage control circuit that utilizes a level-shifter circuit and a switch circuit to isolate a charge pump output terminal from a system voltage source when a charge pump is enabled, and to couple the charge pump output terminal to the system voltage source when the charge pump is disabled. The level-shifter circuit receives the charge pump output voltage as its high voltage supply and the charge pump enable signal as its input signal, and transmits the charge pump output voltage from its output terminal when the charge pump is enabled, and zero volts when the charge pump is disabled. The switch circuit includes a PMOS transistor constructed such that its bulk and source are connected to the charge pump output terminal, and its drain is connected to the system voltage source. The switch circuit also includes a guard ring structure surrounding the PMOS transistor.

Abstract: A voltage control circuit that utilizes a level-shifter circuit and a switch circuit to isolate a charge pump output terminal from a system voltage source when a charge pump is enabled, and to couple the charge pump output terminal to the system voltage source when the charge pump is disabled. The level-shifter circuit receives the charge pump output voltage as its high voltage supply and the charge pump enable signal as its input signal, and transmits the charge pump output voltage from its output terminal when the charge pump is enabled, and zero volts when the charge pump is disabled. The switch circuit includes a PMOS transistor constructed such that its bulk and source are connected to the charge pump output terminal, and its drain is connected to the system voltage source. The switch circuit also includes a guard ring structure surrounding the PMOS transistor.