Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, a charge storage region and the drain region may be positioned on a same side of the photodetection region. In some embodiments, at least one drain layer may be configured to receive incident photons and/or charge carriers via the photodetection region. In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in the plurality of pixels.

Abstract: In some embodiments, an integrated circuit includes multiple charge storage regions configured to receive charge carriers from a photodetection region in response to a single excitation of a sample. In some embodiments, an integrated circuit includes first and second charge transfer paths configured to electrically couple a photodetection region to first and second charge storage regions, with the second charge transfer path bypassing the first charge storage region. In some embodiments, an integrated circuit includes a photodetection region configured to induce an intrinsic electric field having a vector component in at least three substantially perpendicular directions. In some embodiments, an integrated circuit includes multiple transfer gates configured to control charge carrier transfer out of a photodetection region in different directions.

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates.

Abstract: Some aspects relate to integrated devices for obtaining timing and/or spectral information from incident light. In some embodiments, a pixel may include one or more charge storage regions configured to receive charge carriers generated responsive to incident photons from a light source, with charge carriers stored in the charge storage region(s) indicative of spectral and timing information. In some embodiments, a pixel may include regions having different depths, each configured to generate charge carriers responsive to incident photons. In some embodiments, a pixel may include multiple charge storage regions having different depths, and one or more of the charge storage regions may be configured to receive the incident photons and generate charge carriers therein. In some embodiments, a pixel may include an optical sorting element configured to direct at least some incident photons to one charge storage region and other incident photons to another charge storage region.

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a photodetection region and a drain region electrically coupled to the photodetection region, and the photodetection region may be configured to induce an intrinsic electric field in a direction from the photodetection region to the drain region(s). In some embodiments, a charge storage region and the drain region may be positioned on a same side of the photodetection region. In some embodiments, at least one drain layer may be configured to receive incident photons and/or charge carriers via the photodetection region. In some embodiments, an integrated circuit may comprise a plurality of pixels and a control circuit configured to control a transfer of charge carriers in the plurality of pixels.

Abstract: Some aspects relate to an integrated circuit, comprising at least one photodetection region configured to generate charge carriers responsive to incident photons emitted from a sample, at least one charge storage region configured to receive the charge carriers from the photodetection region, and at least one controller configured to obtain information about the incident photons, the information comprising at least one member selected from the group comprising pulse duration and interpulse duration and at least one member selected from the group comprising wavelength information, luminescence lifetime information, and intensity information. In some embodiments, the information comprises at least three, four, and/or five members selected from the group comprising wavelength information, luminescence lifetime information, intensity information, pulse duration information, and interpulse duration information. In some embodiments, the information obtained may be used to identify the sample.

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates.

Abstract: Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

Abstract: Described herein are techniques to reduce or remove the impact of secondary path photons and/or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and/or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and/or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and/or photons.

Abstract: Some aspects relate to an integrated circuit, comprising at least one photodetection region configured to generate charge carriers responsive to incident photons emitted from a sample, at least one charge storage region configured to receive the charge carriers from the photodetection region, and at least one controller configured to obtain information about the incident photons, the information comprising at least one member selected from the group comprising pulse duration and interpulse duration and at least one member selected from the group comprising wavelength information, luminescence lifetime information, and intensity information. In some embodiments, the information comprises at least three, four, and/or five members selected from the group comprising wavelength information, luminescence lifetime information, intensity information, pulse duration information, and interpulse duration information. In some embodiments, the information obtained may be used to identify the sample.

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Aspects of the present disclosure relate to techniques for reducing skew in an integrated device, such as a CMOS imaging device. In some aspects, multiple pixels of an integrated circuit may be configured to receive a same control signal and conduct charge carriers responsive to the control signal substantially at the same time. In some aspects, an integrated circuit may have modulated charge transfer channel voltage thresholds, such as by having different charge transfer channel lengths, and/or a doped portion configured to set a voltage threshold for charge transfer. In some aspects, an integrated circuit may have a via structure having a plurality of vias extending between continuous portions of at least two metal layers. In some aspects, an integrated circuit may include a row of pixels and a voltage source configured to provide a voltage to bias a semiconductor substrate of the integrated circuit along the row of pixels.

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some embodiments, an integrated circuit may comprise a plurality of photodetection regions and one or more intermediate regions between the photodetection regions. In some embodiments, the intermediate regions may comprise bulk semiconductor material that facilitates a transfer of noise charge carriers from the intermediate regions to drain regions associated with each photodetection region. In some embodiments, a drain device may be configured with a gate controlling the flow of charge carriers from the intermediate regions and photodetection regions to drain regions. In some embodiments, an integrated circuit may comprise an array of pixels and a control circuit configured to control a transfer of charge carriers in the array of pixels.

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel, wherein the first pixel is proximate the second pixel in a mirrored configuration. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel that is proximate to the first pixel along a row direction, and a conductive line extending along a column direction that intersects with the row direction, wherein the conductive line is in electrical communication with a first component of the first pixel and a second component of the second pixel.

Abstract: Aspects of the technology described herein relate to improved semiconductor-based image sensor designs. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel, wherein the first pixel is proximate the second pixel in a mirrored configuration. In some aspects, an integrated circuit described herein may include a first pixel and a second pixel that is proximate to the first pixel along a row direction, and a conductive line extending along a column direction that intersects with the row direction, wherein the conductive line is in electrical communication with a first component of the first pixel and a second component of the second pixel.

Abstract: A time-of-flight (TOF) pixel includes a semiconductor material and a photogate disposed proximate to a frontside of the semiconductor material. The photogate is positioned to transfer charge in the semiconductor material toward the frontside in response to a voltage applied to the photogate. A floating diffusion is disposed in the semiconductor material proximate to the frontside of the semiconductor material, and one or more virtual phase implants is disposed in the semiconductor material proximate to the frontside of the semiconductor material. At least one of the one or more virtual phase implants extend laterally from under the photogate to the floating diffusion to transfer the charge to the floating diffusion.

Abstract: The present disclosure provides techniques for improving the rate and efficiency of charge transfer within an integrated circuit configured to receive incident photons. Some aspects of the present disclosure relate to integrated circuits that are configured to induce one or more intrinsic electric fields that increase the rate and efficiency of charge transfer within the integrated circuits. Some aspects of the present disclosure relate to integrated circuits configured to induce a charge carrier depletion in the photodetection region(s) of the integrated circuits. In some embodiments, the charge carrier depletion in the photodetection region(s) may be intrinsic, in that the depletion is induced even in the absence of external electric fields applied to the integrated circuit. Some aspects of the present disclosure relate to processes for operating and/or manufacturing integrated devices as described herein.

Abstract: The present disclosure provides techniques for improving the rate and efficiency of charge transfer within an integrated circuit configured to receive incident photons. Some aspects of the present disclosure relate to integrated circuits that are configured to induce one or more intrinsic electric fields that increase the rate and efficiency of charge transfer within the integrated circuits. Some aspects of the present disclosure relate to integrated circuits configured to induce a charge carrier depletion in the photodetection region(s) of the integrated circuits. In some embodiments, the charge carrier depletion in the photodetection region(s) may be intrinsic, in that the depletion is induced even in the absence of external electric fields applied to the integrated circuit. Some aspects of the present disclosure relate to processes for operating and/or manufacturing integrated devices as described herein.

Abstract: Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates.