Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period Tp to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of Tp/N seconds over a range spanning Tp seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning Tp seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of Tp/(M*N) seconds when the integers N and M are relatively prime.

Abstract: A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

Abstract: The disclosed apparatus includes first and second delay lines, the first delay line having an input tap and a set of n output taps F.sub.1, F.sub.2, . . . F.sub.n, and the second delay line having an input tap and a set of n output taps S.sub.1, S.sub.2, . . . S.sub.n, and each of the output taps has an associated delay interval. A first signal representative of a first event is applied to the input tap of the first delay line, and a second signal representative of a second event is applied to the input tap of the second delay line. The disclosed apparatus further includes a set of n latches L.sub.1, L.sub.2, . . . L.sub.n, and a set of n delay units D.sub.1, D.sub.2, . . . D.sub.n. The output signals generated by taps F.sub.i and S.sub.i are applied to a first input terminal and a second input terminal, respectively, of latch L.sub.i.