Patents by Inventor Eric D. Hornchek

Eric D. Hornchek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6541991
    Abstract: An interface apparatus including a nesting member having a central test area, a positioning member surrounding the test area, and several removable adapters held by the positioning member to expose a selected portion of the test area. Each removable adapter includes a central opening that is sized to receive a corresponding ball grid array integrated circuits (BGA IC). During a first test procedure, a relatively small BGA IC is inserted through the relatively small central opening of a corresponding first adapter. The first adapter is then removed and replaced with a second adapter having a relatively large central opening. A second test procedure is then performed by inserting a relatively large BGA IC through the relatively large central opening formed in the second adapter.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: April 1, 2003
    Assignee: Xilinx Inc.
    Inventors: Eric D. Hornchek, Mohsen H. Mardi
  • Patent number: 6292003
    Abstract: An apparatus and method for testing “chip scale” integrated circuits (IC's) using a vertical probe card mounted on a printed circuit board (PCB). A nesting assembly mounted over the vertical probe card includes alignment walls and an alignment plate including chamfered through holes. The alignment walls are slanted to provide rough alignment of the IC within the nesting assembly, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Tips of formed wire probes extend from the vertical probe card towards the bottom surface of the alignment plate. When the alignment plate is pushed towards the vertical probe card by a device handler, the tips of the wire probes extend through the through-holes and pierce the solder balls of the IC, providing electrical contact between the IC and the PCB.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: September 18, 2001
    Assignee: Xilinx, Inc.
    Inventors: Toby Alan Fredrickson, Eric D. Hornchek
  • Patent number: 5955888
    Abstract: An apparatus and method for testing ball grid array integrated circuits (BGA ICs) including a nesting member resiliently supported on a contactor body via guide shafts. The nesting member includes alignment walls and an alignment plate defining chamfered through-holes. The alignment wall is slanted to provide rough alignment of the IC within the nesting member, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Spring-loaded pogo pins are mounted on a circuit board and have pointed tips extending toward a lower surface of the nesting member alignment plate. When the nesting member is pushed toward the circuit board by a device handler, the pointed tips of the pogo pins extend through the through-holes and pierce the solder balls of the IC, thereby providing electrical contact between the IC and the interface apparatus.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: September 21, 1999
    Assignee: Xilinx, Inc.
    Inventors: Toby Alan Frederickson, Eric D. Hornchek