Patents by Inventor Eric D. Luckowski
Eric D. Luckowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8415212Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.Type: GrantFiled: March 11, 2010Date of Patent: April 9, 2013Assignee: Freescale Semiconductor, Inc.Inventors: James K. Schaeffer, Eric D. Luckowski, Todd C. Bailey, Amy L. Child, Daniel Jaeger, Renee Mo, Ying H. Tsang
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Patent number: 8309419Abstract: A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23) with a first dopant species on a high-k gate dielectric layer (22) in at least the NMOS device area and also forming second capping oxide layer (27) with a second dopant species on a high-k gate dielectric layer (22) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer (22) to form a first fixed charge layer (31) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer (32) in the NMOS device area of the high-k gate dielectric area.Type: GrantFiled: February 4, 2009Date of Patent: November 13, 2012Assignee: Freescale Semiconductor, Inc.Inventors: James K. Schaeffer, Eric D. Luckowski
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Publication number: 20110223756Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.Type: ApplicationFiled: March 11, 2010Publication date: September 15, 2011Inventors: James K. Schaeffer, Eric D. Luckowski, Todd C. Bailey, Amy L. Child, Daniel Jaeger, Renee Mo, Ying H. Tsang
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Publication number: 20100197128Abstract: A method and apparatus are described for fabricating single metal gate electrodes (35, 36) over a high-k gate dielectric layer (31, 32) that is separately doped in the PMOS and NMOS device areas (96, 97) by forming first capping oxide layer (23) with a first dopant species on a high-k gate dielectric layer (22) in at least the NMOS device area and also forming second capping oxide layer (27) with a second dopant species on a high-k gate dielectric layer (22) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer (22) to form a first fixed charge layer (31) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer (32) in the NMOS device area of the high-k gate dielectric area.Type: ApplicationFiled: February 4, 2009Publication date: August 5, 2010Inventors: James K. Schaeffer, Eric D. Luckowski
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Patent number: 7751177Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.Type: GrantFiled: April 28, 2009Date of Patent: July 6, 2010Assignee: Freescale Semiconductor, IncInventors: Douglas R. Roberts, Eric D. Luckowski, Shahid Rauf, Peter L. G. Ventzek
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Publication number: 20090279226Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.Type: ApplicationFiled: April 28, 2009Publication date: November 12, 2009Applicant: Freescale Semiconductor, IncInventors: Douglas R. Roberts, Eric D. Luckowski, Shahid Rauf, Peter L.G. Ventzek
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Patent number: 7579282Abstract: A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).Type: GrantFiled: January 13, 2006Date of Patent: August 25, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Shahid Rauf, Olubunmi O. Adetutu, Eric D. Luckowski, Peter L. G. Ventzek
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Patent number: 7534693Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.Type: GrantFiled: January 4, 2006Date of Patent: May 19, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Douglas R. Roberts, Eric D. Luckowski, Shahid Rauf, Peter L. G. Ventzek
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Patent number: 6916669Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.Type: GrantFiled: March 3, 2003Date of Patent: July 12, 2005Inventors: Robert E. Jones, Carole C. Barron, Eric D. Luckowski, Bradley M. Melnick
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Patent number: 6790719Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with the a gate dielectric. The N channel gate stack and a portion of the P channel gate stack are etched by a dry etch. The etch of P channel gate stack is completed with a wet etch. The wet etch is very selective to the gate dielectric and to the second metal type so that the N channel transistor is not adversely effected by completing the etch of the P channel gate stack.Type: GrantFiled: April 9, 2003Date of Patent: September 14, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Olubunmi O. Adetutu, Eric D. Luckowski, Srikanth B. Samavedam, Arturo M. Martinez, Jr.
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Publication number: 20030151079Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.Type: ApplicationFiled: March 3, 2003Publication date: August 14, 2003Inventors: Robert E. Jones, Carole C. Barron, Eric D. Luckowski, Bradley M. Melnick
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Patent number: 6555858Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (250), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.Type: GrantFiled: November 15, 2000Date of Patent: April 29, 2003Assignee: Motorola, Inc.Inventors: Robert E. Jones, Carole C. Barron, Eric D. Luckowski, Bradley M. Melnick