Abstract: A full wave rectifier (270) for use as part a differential signal detector (400) detects both high and low envelopes of differential signals (RXa, RXb) at a pair of differential inputs (202, 204) and provides a sense signal (VSENSE) at an output (220) thereof. The differential signal detector (400) includes both the full wave rectifier (270) and a voltage reference source (260) having a circuit architecture in common, and a comparator for comparing the sense signal (VSENSE) with a reference voltage (VREF). The circuit configuration of both the full wave rectifier (270) and the voltage reference source (260) include first and second differential input circuits (271 and 273, 261 and 263) each including a pair of field effect transistors (2722, 2742 and 2762, 2782; 2622, 2642 and 2662, 2682) of different conductivity type having respective source terminals (2728, 2748; 2768, 2788; 2628, 2648; 2668, 2688) coupled together.

Abstract: A system and method are provided for augmenting frequency tuning resolution in an L-C oscillatory circuit which comprises a source of electrical energy, and a tuned section energized by said source of electrical energy for oscillatory conduction of a resonant current therethrough. The tuned section includes an inductor portion extending in substantially looped manner between first and second connection points to define at least one turn. A primary capacitor portion is connected across at least a primary segment of the conductive member delineated by the first and second connection points. The tuned section further includes a secondary capacitor portion connected across a secondary segment of the conductive member intermediately tapped from the primary segment.

Abstract: A voltage controlled oscillator amplitude control circuit has a voltage controlled oscillator circuit to output an oscillating signal having a controlled amplitude. It also has a control circuit to control the amplitude of the oscillating signal by providing a dominant pole, a filtering function, rectification, and a gain at a single node of the circuit.

Abstract: An improved transmitter capable of achieving high linearity with minimal power dissipation is disclosed, comprising a digital phase splitter and an output stage. The digital phase splitter includes a positive phase digital-to-analog converter (DAC) for converting the positive phase portion of a set of input digital data into an analog signal, and a negative phase DAC for converting the negative phase portion of the set of input digital data into another analog signal. The analog signals from the phase splitter are passed to the output stage for transmission onto a transmission medium. The transmitter may be operated in low power dissipation mode. Because the phases of the input digital signal are split in the digital domain prior to the output stage, the output stage experiences minimal crossover distortion. Consequently, the transmitter is able to minimize power dissipation without suffering from poor linearity performance.

Abstract: A multi-bit analog-to-digital converter architecture, which during normal operation behaves like a single-bit converter, thus sharing the high linearity and low distortion properties of the simpler system. When a high input signal is applied, a second bit is triggered and the system behaves like a more complex multi-bit system, providing system stability where a single-bit comparator would overload and the system would become unstable. During normal operation, a single-bit converter is sufficient to stabilize the system. When the input is a large, sustained signal (relative to the full scale of the converter) this single-bit approach is not sufficient to maintain system stability. Thus, if the input to the analog-to-digital converter is close to its maximum or minimum range (implying a large positive or negative input signal) a second bit is triggered, providing stable linearity where the signal-to-noise ratio of a conventional sigma-delta converter would rapidly drop off.

Abstract: A method and apparatus are provided for transitioning a power converter between a switched mode of operation and a linear regulator mode of operation. The power converter operates according to one or more intermediate modes of operation in which the switched mode and linear regulator modes cooperate to produce a shared power converter output. The power converter transitions between the various modes of operation in response to changes in circuit parametric conditions as defined by a series of state transition diagrams. Power converter output voltage is maintained in regulation during all modes of operation and transitions therebetween. The method and apparatus includes an integrated device that may be operated as a switch or a variable resistance device.

Abstract: A low-power controller for a discontinuous switched mode power converter. The controller has an inductor current sensing circuit to measure the inductor current flowing through an inductive charge storage element as well as an output voltage sensing circuit to monitor output voltage. The controller monitors both the converter output voltage and the inductor current and uses this information to modulate a peak inductor current trip point and controller switching frequency according to a control law curve in order to regulate converter output voltage. The controller prevents the switching frequency from falling below a predetermined minimum frequency. The control law curve is selectable to specify controller operation according to a desired combination of minimum switching frequency and maximum peak inductor current.

Abstract: A high-amperage current sensor is disclosed which is suitable for use in an automotive electrical system and which is operatively unaffected by changes in ambient temperature. The current sensor utilizes a shunt assembly having at least one low-resistance shunt element connectable in line between a source of electrical energy and a load. Circuitry preferably configured on an application specific integrated circuit measures voltage drop across the shunt element due to current flow. As a result, an output signal is produced which may be fed to external circuitry for further processing. In presently preferred embodiments, the sensor may comprise analog circuitry producing an analog output signal and/or digital circuitry producing a digital output signal.

Abstract: A two-loop superconducting sigma-delta analog-to-digital converter includes a first superconducting inductor to which the analog signal is applied. A resistor converts to current in the first inductor to a voltage which is applied to a second superconducting inductor. The current in the second inductor, which increases quadradically with time, is applied to an overdamped Josephson junction which kicks back a single quantum voltage pulse each time its critical current is exceeded. This pulse reduces the current in the second inductor and serves as a digital ONE output. The pulses are also applied to an underdamped Josephson junction in a feedback pulse generator which latches at its gap voltage for the remainder of a half cycle of an ac bias current.

Abstract: A superconducting sigma-delta analog-to-digital converter utilizes a superconducting inductor as the integrator and a Josephson junction connected in series between the inductor and ground as the quantizer. A SQUID generates sampling pulses at a selected GHz frequency which add to the inductor current flowing through the Josephson junction. When the combined current through the Josephson junction exceeds the critical current of the Josephson junction, a voltage pulse is generated which kicks back into the inductor to reduce the inductor current. The voltage across the Josephson junction is, therefore, a one bit digital representation of the analog signal. This one bit digital signal is converted to a multi-bit digital signal preferably by a decimator having superconducting circuits which reduce the frequency of the multi-bit digital signal to a frequency which can be further processed by semiconductor processors. Preferably, a weighting function is utilized in a conversion to improve accuracy.

Abstract: The present invention is a multimode sensor system that transmits power down a common bus coaxial cable typically using an alternating current power source. Each remote unit connected to the coaxial cable and through an isolation transformer converts the alternating current power to direct current power for an integrated circuit bus interface. The interface is connected to the sensors. The interface is externally pin programmable to provide a carrier at a frequency for a channel assigned to the remote unit. The carrier is provided by a ripple counter producing a frequency divided signal compared to a fixed reference frequency, where the result of the comparison controls a voltage controlled oscillator. When plural low frequency analog signals are to be transmitted over the common bus, an on-chip multiplexer multiplexes the signals to an off-chip, external analog-to-digital converter.

Abstract: An analog-to-digital converter having error correction in the digital stages of the converter. A calibration microprocessor executes a correction value program prior to, or interspaced with, the normal operation of the converter. From either of two calibration programs, appropriate digital correction values are stored into a digital memory. The analog input signal is converted to a digital signal by a main range analog-to-digital converter, with the output of the converter addressing the memory containing the error correction values. The main range digital value is reconverted to an analog signal which is compared to the original input signal to determine the difference therebetween. This analog difference is converted to a digital signal and combined with the main range digital signal and the addressed correction values to produce the digital output signal of the conversion system.

Abstract: Double complementary storage is provided for a single binary digit in a quad store cross-tie memory. A correlated double sampling signal processing system is used to increase data signal level and facilitate discrimination in cross-tie memories. A method is also provided for accomplishing write and read functions in a quad store cross-tie memory using only a single pulse for either function. A set of four memory elements, arranged in two row-aligned complementary pairs, stores a single data bit, and is under four column conductors for reading data, two row conductors, and a write conductor for writing data.

Abstract: The present invention is a multimode sensor system that transmits power down a common bus coaxial cable typically using an alternating current power source. Each remote unit connected to the coaxial cable and through an isolation transformer converts the alternating current power to direct current power for an integrated circuit bus interface. The interface is connected to the sensors. The interface is externally pin programmable to provide a carrier at a frequency for a channel assigned to the remote unit. The carrier is provided by a ripple counter producing a frequency divided signal compared to a fixed reference frequency, where the result of the comparison controls a voltage controlled oscillator. When plural low frequency analog signals are to be transmitted over the common bus, an on-chip multiplexer multiplexes the signals to an off-chip, external analog-to-digital converter.

Abstract: A magnetoresistive random access memory array and signal processing system which provides an improved signal to noise ratio. The basic memory complex associated with the storage of a single binary digit is a quad of memory elements or cells which are addressed in complementary fashion. The enhanced read-out signal discrimination is had by utilizing a double-correlated double-sampling differential signal processing system in which complementary data is serially passed through the same path with repeated high-speed differencing which greatly reduces nonuniformity fixed patterns as well as correlated low frequency temporal noise.

Abstract: An improved latching-type comparator operative in a selected one of two exclusive states is disclosed. In one state, the operational state, a gain stage is rendered operative to amplify at least one intermediate current signal generated by an input stage in response to the comparison of a pair of input signals. At least one drive current signal is generated by the gain stage in response to the comparison and is buffered by a corresponding buffer stage to render both an output signal and a signal representative thereof. In the other state, a latch stage is rendered operative unresponsive to the comparison and governed by the signal representative of the output signal to sustain the drive current signal in a state to latch the output signal. A switching stage governed by at least one latch signal effects the selection between the gain and latch stages by conducting operating current exclusively from the selected stage to a constant current stage.