Abstract: A system and method are provided for generating an adaptive clock signal, configured to track prevailing operating conditions within an integrated circuit. The method comprises transmitting a first signal edge to a row of cells within a memory instance, waiting for two or more selected cells within the row of cells to propagate corresponding responses based on the first signal edge, and generating a memory delay signature signal edge based on the corresponding responses. The adaptive clock signal is generated based on the delay signature signal edge.

Abstract: A system and method are provided for generating an adaptive clock signal, configured to track prevailing operating conditions within an integrated circuit. The method comprises transmitting a first signal edge to a row of cells within a memory instance, waiting for two or more selected cells within the row of cells to propagate corresponding responses based on the first signal edge, and generating a memory delay signature signal edge based on the corresponding responses. The adaptive clock signal is generated based on the delay signature signal edge.

Abstract: A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage.

Abstract: A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage.

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Abstract: A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entries producing those false matches. While the entries producing a match should have the same index location, errors might cause those match lines to have an offset. If so, the present CAM, through use of duplicative sets of CAM locations, will detect the offset and thereafter the values in each index location that produces a match, along with the corresponding parity or error detection encoding bit(s). If the parity or error detection encoding bit(s) indicate an error in a particular entry, then that error is located and the corresponding entry at the same index within the other, duplicative set of CAM locations is copied into the that erroneous entry.

Abstract: A ternary content addressable memory (TCAM) cell (100) can include two memory elements (102-0 and 102-1) with a single bit line (106-0 and 106-1) per memory element. A TCAM cell (100) can also include a compare stack (104) and two word lines (114 and 116) that can connect to each memory element (102-0 and 102-1). The memory elements (102-0 and 102-1) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements (102-0 and 102-1) to the pre-write potential prior to providing write data via the bit lines (106-0 and 106-1).

Abstract: A content addressable memory (CAM) device (200) can equalize a potential between a match line (202) and corresponding pseudo-supply (PVSS) line (204) in a pre-sense operation. In a sense operation, a sensing device (P4) can determine a match condition exists when the match line (202) potential varies from the PVSS line (204) potential. Complementary compare data lines (CD and BCD) can be equalized with one another in a pre-sense operation, while one compare data line (CD or BCD) can be equalized with bit lines (BB1 and/or BB2) in the sensing operation.

Abstract: A method and an apparatus to generate static logic level outputs without a direct connection from a MOS transistor gate to either a power supply or ground supply are described. The apparatus may include a first circuit comprising a static logic level output. The apparatus may further include a second circuit coupled to the first circuit to drive the first circuit. The second circuit may comprise at least one of a latch and a feedback device.

Abstract: A sense amplifier for a content addressable memory (CAM) device can utilize charge sharing between a match line and a pseudo-supply line to indicate a mis-match indication. A sense amplifier (200) can include match line (202) that can be precharged to a high supply potential (VCC), a sense node (206), and a pseudo-VSS (PVSS) line (204) that can be precharged to a low supply potential (VSS). In a match result, match line (202) can remain precharged, keeping sense device (P2) turned off, and sense node (206) remains low, generating a low output signal (SAOUT). In a mis-match result, match line (202) and sense node (206) can be equalized. A resulting drop in match line (202) potential can turn on sense device (P2), and sense node (206) can be pulled high. As a result, output signal (SAOUT) can be driven high.

Abstract: According to one embodiment, a content addressable memory (CAM) (100) can include a number of ordinary rows (102-0 to 102-n) that provide ordinary match indications (Match0 to Matchn) as well as redundant rows (108-0 and 108-1) that can provide redundant match indications (RMatch0 and RMatch1). If an ordinary row (102-0 to 102-n) is defective, a redundancy multiplexer (114-0 to 114-n) can be switched to provide a redundant match indication (RMatch0 and RMatch1) as an input to a priority encoder (118) instead of the ordinary match indication from the defective ordinary row.

Abstract: A content addressable memory (CAM) (100) can include a number of CAM entries (102-0 to 102-n). Match indications from CAM entries (102-0 to 102-n) and mismatch indications from complementing circuits (106-0 and 106-n) can be supplied to a switching circuit (108). Mismatch indications can indicate if an entry mismatches data when compared with a comparand (104). In one mode of operation, a switching circuit (108) can provide match indications on a number of switch outputs (SW0 to SWn). In another mode of operation, switching circuit (108) can provide mismatch indications on a number of switch outputs (SW0 to SWn).

Abstract: According to one embodiment, a content addressable memory (CAM) (100) can include a number of CAM entries (102-0 to 102-n) and corresponding status stores (106-0 and 106-n). Match indications from the CAM entries (102-0 to 102-n) and status information from status stores (106-0 and 106-n) can be supplied to a switching circuit (108). Status information can indicate if an entry stores valid or invalid data. In one mode of operation, the switching circuit (108) can provide match indication values on a number of switch outputs (SW0 to SWn). In another mode of operation, the switching circuit (108) can provide status information on a number of switch outputs (SW0 to SWn).

Abstract: According to one embodiment, a content addressable memory (CAM) can include at least one match line (404), series-coupled transistor pairs comprising match transistors (402-0 to 402-n) and switch devices (422-0 to 422-n), bit match indicator signals (406-0 to 406-n), mask cell value signals (412-0 to 412-n), a match line precharge limiting device (414), a match line precharge control device (416) and an amplifier circuit (432). This configuration can allow for the regulation of the match line (404) discharge path through a discharge control device (410) and a match indication feedback device (426). This, in turn, can allow for match line (404) precharging while at least one of the bit match indicator signals (406-0 to 406-n) is in an intermediate, or approximately half-VDD, level that is consistent with relatively low power precharging of the applied comparands.

Abstract: A content addressable memory that may have reduced charge consumption when switching compare lines is disclosed. According to one embodiment, a content addressable memory (CAM) (300) with paired compare lines (CMP and CMP\) can include an equalization circuit (320) between the two compare lines (CMP and CMP\). An equalization circuit (320) can enter a low-impedance mode when an equalization control signal (EQU\) is in one state and enter a high-impedance mode when an equalization control signal (EQU\) is in another state. An equalization control signal (EQU\) may be governed by an output pulse of a transition detector (312).

Abstract: A CAM cell array (100) that can provide a longest prefix matching operation without necessarily requiring data values to be stored in a particular order. A comparand value can be applied to a CAM cell array (100) to generate ternary match indications. The mask/prefix data values of ternary match indications can be combined to generate a longest prefix value. The longest prefix value can be compared with the mask/prefix data values of the ternary match indications to indicate a data value having a longest prefix match with the comparand value.

Abstract: A combinational encoder (100) according to one embodiment is disclosed. The combinational encoder (100) can be used with an address encoder (300) to provide a compact priority encoder. The combinational encoder (300) receives a number of input signals (MATCH_IN0-MATCH_IN3) and provides a like number of output signals (MATCH_OUT0-MATCH_OUT3). Unlike a conventional priority encoder, which activates a single output signal in response to various input signal combinations, the combinational encoder (100) provides multiple active output signals in response to particular combinations of input signals. When applied to an appropriate address encoder (300), the multiple active output signals generate address values reflecting the desired priority of the input signals.

Abstract: According to one embodiment, a priority encoder (PE)/read-only-memory (ROM) combination circuit (200) includes detect circuits (206-xy) and passgate circuits (208-xy) arranged into rows (202-x) and columns (202-y). Detect circuits (206-xy) of the same column can be activated by a corresponding input signal (M0 to M7). When a detect circuit (206-xy) of a column (202-y) is activated, the passgates (208-xy) of the same column are disabled, preventing any lower priority active input signals (M0 to M7) from propagating further into the circuit.

Abstract: A content addressable memory (CAM) that is capable of providing multiple word matching is disclosed. According to one embodiment, a CAM (200) includes a word array (206) of data word registers (208-0 to 208-ni). Each data word register (208-0 to 208-ni) provides a word match value (MATCH0-MATCHni) that indicates if an applied comparand value is the same as a data word stored within a data word register (208-0 to 208-ni). Word match values (MATCH0-MATCHni) are received by a match detect circuit (202) that provides a number of encoding values (ENC0-ENCni). In a single word match mode, a comparand value is applied and the encoding values (ENC0-ENCni) can represent single word match values. In a multiple word match mode, a sequence of comparand values are applied and the resulting word match values stored. The resulting encoding values (ENC0-ENCni) can represent the logical combination of multiple word match values.

Abstract: According to one embodiment, a multiple signal detect circuit (100) can include a detect node (102) and a reference node (104). The potential of the detect node (102) can be discharged (or charged) at a rate that depends upon the number of active input signals (M1 to Mn). The potential of the reference node (104) can be discharged (or charged) at a reference rate. The reference rate can be greater than the rate at which the detect node (102) is discharged (or charged) when one input signal is activated, and less than the rate at which the detect node (102) is discharged (or charged) when two input signals are activated. A differential voltage between the detect node (102) and reference node (104) can be amplified by an amplifier (110).