Abstract: A test device for testing integrated electronic chips (EC) includes: a first processor; an interface for interfacing the first processor with a plurality of other circuits; and a second processor coupled to the first processor. In the test device, at least one of the plurality of other circuits is formed on the integrated electronic chip being tested. The interface includes a first scan path having a first string of first cells formed on the integrated electronic chip. The first string of first cells includes a plurality of serially connected first read buffers, a respective one of the first read buffers being provided in each first cell, for latching data and for transferring data between the at least one circuit of the plurality of other circuits and the first processor.