Abstract: A driver electronic circuit for a pulse amplitude modulation transmitter includes a plurality of transmission lanes. Each transmission lane is configured to independently generate a current output corresponding to data input into each transmission lanes. The driver electronic circuit also includes a summing node configured to sum the output currents from the plurality of transmission lanes. The driver electronic circuit further includes one feedback loop circuit coupled to the plurality of transmission lanes configured to control the currents of each said current outputs. The driver electronic circuit may be configured to drive a vertical-cavity surface-emitting laser for optical communication.

Abstract: A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency PWM (or PFM) signals and still share the same ring oscillator.

Abstract: A multichannel digital pulse width modulator/digital pulse frequency modulator uses a single ring oscillator that is shared by multiple channels. The ring oscillator has taps that can be used for least significant bit (LSB) precision of the generated PWM signal. The ring oscillator also produces a ring clock that is used to synchronize logic in the channels. Since the logic in the channels are synchronized by the ring clock, the channels can each independently produce different frequency PWM (or PFM) signals and still share the same ring oscillator.

Abstract: A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.

Abstract: A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outputs so as to prevent premature pulse width reset. Jitter tolerance look ahead circuits can prevent jitter from causing premature reset of pulse width modulated signals. The pulse width modulators can include multiple alternately used multiplexers so that the operation of the pulse width modulators is not affected by the load time of the multiplexers.

Abstract: Systems and methods for tuning a phase locked loop (PLL) having a segmented voltage controlled oscillator (VCO) to an input frequency are provided. The PLL is reset and its VCO is coarse tuned until the input frequency is within a first predetermined threshold of the VCO center frequency. The input frequency is then compared to a clock reference signal to determine whether the input frequency has stabilized. After the input frequency has stabilized, the input frequency is continuously monitored by comparing it to the clock reference signal to determine whether the input frequency is varying, and if the input frequency is varying by more than a second predetermined threshold, then the PLL is reset.

Abstract: A delay locked loop includes a triangle wave generator circuit coupled to a serial clock signal for generating a triangular wave signal. A phase interpolator coupled to the triangular wave signal and a weighting signal generates an interpolated clock phase signal, and a phase detector receives serial data and the interpolated clock phase signal and generates a retimed serial data signal.

Abstract: A tunable ring oscillator, in accordance with the teachings described herein, may include one or more delay circuits having a coarse tuning circuitry and a fine tuning circuitry. The coarse tuning circuitry may be used to set one of a minimum time delay or a maximum time delay as a function of a coarse tuning input. The fine tuning circuitry may be used to adjust between the minimum time delay and the maximum time delay as a function of a fine tuning input.

Abstract: A tunable ring oscillator, in accordance with the teachings described herein, may include one or more delay circuits having a coarse tuning circuitry and a fine tuning circuitry. The coarse tuning circuitry may be used to set one of a minimum time delay or a maximum time delay as a function of a coarse tuning input. The fine tuning circuitry may be used to adjust between the minimum time delay and the maximum time delay as a function of a fine tuning input.