Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

Abstract: An apparatus includes a photodetector configured to generate an electrical current based on received illumination. The apparatus also includes a capacitor transimpedance amplifier (CTIA) unit cell having (i) an amplifier configured to receive the electrical current and a reference voltage, (ii) a feedback capacitor coupled in parallel across the amplifier, and (iii) a reset switch coupled in parallel across the feedback capacitor. The apparatus further includes an event detector configured to sense a high-energy event affecting the photodetector. In addition, the apparatus includes a switchable clamp coupled across inputs of the amplifier, where the event detector is configured to close the switchable clamp in response to sensing the high-energy event.

Abstract: A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

Abstract: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

Abstract: A focal plane array includes a mosaic integrated circuit device having a plurality of discrete integrated circuit tiles mounted on a motherboard. The focal plane array includes an optically continuous detector array electrically connected to the mosaic integrated circuit device with an interposer disposed therebetween. The interposer is configured to adjust a pitch of the continuous detector array to match a pitch of each of the plurality of discrete integrated circuit tiles so that the optical gaps between each of the plurality of integrated circuit tiles on the motherboard are minimized and the detector array is optically continuous, having high yield over the large format focal plane array.

Abstract: A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.

Abstract: A pixel includes a detector that changes its operating characteristics based on incident energy, an integration capacitor arranged to discharge stored charge through the detector based on changes in the operating characteristics, and an floating gate injection device disposed between the photo-diode and the integration capacitor that controls flow of the charge from the integration capacitor to the detector. The floating gate injection device has a gate, a source electrically coupled to the detector at a first node, and a drain electrically coupled to the integration capacitor. The gate has a control voltage (VT) stored therein to set to a per-pixel bias gate voltage to control a detector bias voltage of the detector at the first node.

Abstract: A digital unit-cell included in an imaging system includes a light sensor configured to generate an electrical charge in response to receiving light, and an energy storage circuit configured to establish a first parasitic capacitance and second large capacitance to store the electrical charge. The digital unit-cell further includes a gain selection circuit and a dual-mode comparator. The gain selection circuit is configured operate in a first mode to invoke the first capacitance and a second mode to invoke the second capacitance. The dual-mode comparator is configured to operate in a first reset mode that generates a first reset signal having a first pulse duration and a second reset mode that generates a second reset signal having a second pulse duration that is a longer than the first pulse duration.

Abstract: A method includes repeatedly charging and discharging a capacitor, where the capacitor is charged based on illumination received at a pixel. The method also includes comparing a voltage stored on the capacitor with a reference voltage using a comparator. The method further includes incrementing or decrementing a first counter value of a first counter each time a comparator output indicates that the capacitor voltage has reached the reference voltage during a first period of time. The method also includes incrementing or decrementing a second counter value of a second counter each time the comparator output indicates that the capacitor voltage has reached the reference voltage during multiple smaller second periods of time within the first period of time. In addition, the method includes resetting the second counter for each second period of time and generating a pixel event indicator in response to the second counter value obtaining a value indicative of a bright intensity event.

Abstract: A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.

Abstract: An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.

Abstract: An image detector includes an array of detector unit cells including a plurality of unit cells and a plurality of single slope analog to digital converters (SSADCs). Each of the plurality of SSADCs is coupled to an output of a different one of the unit cells. Each each of the plurality of SSADCs includes: a comparator having a positive input and a negative input and a comparator output, the comparator being contained in a first layer; and a counter coupled to the comparator output and contained in a second layer. The counter is electrically coupled to the comparator with a through a silicon via.

Abstract: Microbolometer arrays incorporating per-pixel dark reference structures for non-uniformity correction.

Abstract: A method includes repeatedly charging and discharging a capacitor, where the capacitor is charged based on illumination received at a pixel. The method also includes comparing a voltage stored on the capacitor with a reference voltage using a comparator. The method further includes incrementing or decrementing a first counter value of a first counter each time a comparator output indicates that the capacitor voltage has reached the reference voltage during a first period of time. The method also includes incrementing or decrementing a second counter value of a second counter each time the comparator output indicates that the capacitor voltage has reached the reference voltage during multiple smaller second periods of time within the first period of time. In addition, the method includes resetting the second counter for each second period of time and generating a pixel event indicator in response to the second counter value obtaining a value indicative of a bright intensity event.

Abstract: A method includes generating an intensity value based on illumination received at a pixel of an imaging system. The intensity value is generated by integrating values using a first counter of a detector during a first period of time. The method also includes integrating the values repeatedly during smaller second periods of time within the first period of time using a second counter of the detector. The second counter has a lower bit resolution than the first counter. The method further includes resetting the second counter for each of the second periods of time. In addition, the method includes generating a pixel event indicator in response to the second counter outputting a specified value. The method may also include determining whether one or more neighboring detectors also generated one or more pixel event indicators and generating an event indicator when the one or more neighboring detectors also generated the one or more pixel event indicators.

Abstract: According to one aspect, a Read-Out Integrated Circuit (ROIC) with integrated Compressive Sampling (CS) is provided. The ROIC includes an input to couple to a photodetector array including a plurality of photodetectors and is configured to generate compressed image data by sampling and summing the values of the plurality of photodetectors consistent with a set of Compressive Sampling Measurement Matrices and provide the resulting coded aggregates to a signal processor as compressed image data.

Abstract: A method includes generating an intensity value based on illumination received at a pixel of an imaging system. The intensity value is generated by integrating values using a first counter of a detector during a first period of time. The method also includes integrating the values repeatedly during smaller second periods of time within the first period of time using a second counter of the detector. The second counter has a lower bit resolution than the first counter. The method further includes resetting the second counter for each of the second periods of time. In addition, the method includes generating a pixel event indicator in response to the second counter outputting a specified value. The method may also include determining whether one or more neighboring detectors also generated one or more pixel event indicators and generating an event indicator when the one or more neighboring detectors also generated the one or more pixel event indicators.

Abstract: According to one aspect, a Read-Out Integrated Circuit (ROIC) with integrated Compressive Sampling (CS) is provided. The ROIC includes an input to couple to a photodetector array including a plurality of photodetectors and is configured to generate compressed image data by sampling and summing the values of the plurality of photodetectors consistent with a set of Compressive Sampling Measurement Matrices and provide the resulting coded aggregates to a signal processor as compressed image data.

Abstract: A unit cell for use in an imaging system may include an absorber layer of semiconductor material formed on a semiconductor substrate, at least one contact including semiconductor material formed on the semiconductor substrate and electrically coupled to the absorber layer, and a cap layer of semiconductor material formed on the semiconductor substrate and electrically coupled to and formed between the absorber layer and the at least one contact. The absorber layer may be configured to absorb incident photons such that the absorbed photons excite electrons in the absorber layer to generate a photocurrent. The at least one contact may be configured to conduct the photocurrent to one or more electrical components external to the unit cell. The cap layer may be configured to conduct the photocurrent between the absorber layer and the at least one contact.

Abstract: A unit cell for use in an imaging system may include an absorber layer of semiconductor material formed on a semiconductor substrate, at least one contact including semiconductor material formed on the semiconductor substrate and electrically coupled to the absorber layer, and a cap layer of semiconductor material formed on the semiconductor substrate and electrically coupled to and formed between the absorber layer and the at least one contact. The absorber layer may be configured to absorb incident photons such that the absorbed photons excite electrons in the absorber layer to generate a photocurrent. The at least one contact may be configured to conduct the photocurrent to one or more electrical components external to the unit cell. The cap layer may be configured to conduct the photocurrent between the absorber layer and the at least one contact.