Abstract: A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract: The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner.

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract: The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) cavity includes forming a first sacrificial cavity layer over a wiring layer and substrate. The method further includes forming an insulator layer over the first sacrificial cavity layer. The method further includes performing a reverse damascene etchback process on the insulator layer. The method further includes planarizing the insulator layer and the first sacrificial cavity layer. The method further includes venting or stripping of the first sacrificial cavity layer to a planar surface for a first cavity of the MEMS.

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract: A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Abstract: A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Abstract: The instant invention is a method of polishing a substrate including contacting a substrate having at least one metal layer including copper with a chemical-mechanical polishing composition. The CMP composition includes an abrasive, a surfactant, an oxidizer, an organic acid including polyacrylic acid or polymethacrylic acid, a corrosion inhibitor, and a liquid carrier. A portion of the copper in the metal layer is abraded to polish the substrate. A second CMP composition contacts the abraded substrate, the second acrylate free composition including an abrasive, a surfactant, an oxidizer, and a corrosion inhibitor, and a liquid carrier. Any dendrites that may have formed on the substrate are removed through abrasion.

Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

Abstract: A patterned portion of a patterned semiconductor substrate is removed by abrasive mechanical planarization employing an abrasive pad but without employing any slurry. Preferably, water is supplied to enhance the removal rate during the mechanical planarization. The removal rate of material is substantially independent for common materials employed in back-end-of-line (BEOL) semiconductor materials, which enables non-selective removal of the material containing metallization structures. The removal rate of silicon is lower than the removal rate for the BEOL semiconductor materials, enabling a self-stopping planarization process.

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract: In the course of forming a resistor in the back end of an integrated circuit, an intermediate dielectric layer is deposited and a trench etched through it and into a lower dielectric layer by a controllable amount, so that the top of a resistor layer deposited in the trench is close in height to the top of the lower dielectric layer; the trench is filled and the resistor layer outside the trench is removed, after which a second dielectric layer is deposited. Vias passing through the second dielectric layer to contact the resistor then have the same depth as vias contacting metal interconnects in the lower dielectric layer. A tri-layer resistor structure is employed in which the resistive film is sandwiched between two protective layers that block diffusion between the resistor and BEOL ILD layers.

Abstract: A solution for forming a polishing slurry, the polishing slurry and related methods are disclosed. The solution for forming a polishing slurry may include 1 H-benzotriazole (BTA) dissolved in an ionic surfactant such as a sodium alkyl sulfate solution, and perhaps a polyacrylic acid (PAA) solution. The solution can be filtered and used in a polishing slurry. This approach to solubilizing BTA results in a high BTA concentration in a polishing slurry without addition of foreign components to the slurry or increased safety hazard. In addition, the solution is easier to ship because it is very stable (e.g., can be frozen and thawed) and has less volume compared to conventional approaches. Further, the polishing slurry performance is vastly improved due to the removal of particles that can cause scratching.

Abstract: A method of forming a structure, an array of structures and a memory cell, the method of fabricating a structure, including: (a) forming a trench in a substrate; (b) depositing a first layer of polysilicon on a surface of the substrate, the first layer of polysilicon filling the trench; (c) chemical-mechanical-polishing the first layer of polysilicon at a first temperature to expose the surface of the substrate; (d) removing an upper portion of the first polysilicon from the trench; (e) depositing a second layer of polysilicon on the surface of the substrate, the second layer of polysilicon filling the trench; and (f) chemical-mechanical-polishing the second layer of polysilicon at a second temperature to expose the surface of the substrate, the second temperature different from the first temperature.

Abstract: A detection system and method including a means for performing a test on a semiconductor device and obtaining test data therefrom. The semiconductor device includes an insulating layer, a hard mask layer on a surface of the insulating layer, and a plurality of electrically conductive lines within a trench in the insulating layer. The insulating layer comprises a first dielectric material. The hard mask layer comprises a second dielectric material. The dielectric constant of the second dielectric material exceeds the dielectric constant of the first dielectric material or the second dielectric material comprises an element that is not comprised by the first dielectric material. The test data is a function of a spatial distribution of the hard mask layer on the surface of the insulating layer. The detection system and method includes a means for determining from the test data a measure of the spatial distribution of the hard mask layer on the surface of the insulating layer.

Abstract: A method for forming a semiconductor structure includes supplying a structure having an exposed last metalization layer, cleaning the last metalization layer, forming a silicide in a top portion of the last metalization layer and forming a terminal over the silicide.