Patents by Inventor Eric J. Whitesell

Eric J. Whitesell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958273
    Abstract: A decorative, nonwoven laminate and a method of forming, including a first side of a first nonwoven affixed to one or both of a) a first side of a polymeric sheet or b) a second nonwoven, wherein the first nonwoven exhibits a basis weight of 15 g/m2 to 2500 g/m2 and the second nonwoven exhibits a basis weight of 15 g/m2 to 1200 g/m2; and a colorant deposited on a second side of the first nonwoven. A topical coating may or may not be applied to improve durability of the printed surface layer. The decorative nonwoven laminate may also amount to a single layer of the first nonwoven, which then includes a layer of colorant and a topical coating over the colorant and single nonwoven layer.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 16, 2024
    Assignee: AURIA SOLUTIONS UK I LTD.
    Inventors: Kenneth Mitchell Whitesell, Jr., Sean Bracken Simmons, Ernest Franklin Wilson, Tyler M. Heath, Timothy J. Allison, Eric Staudt
  • Patent number: 5537624
    Abstract: A method implemented in hardware logic for transforming data from one bus dth to another includes the steps of: 1) selectively latching data having p1 words each having a q1 width, where p1 and q2 are positive integers; and 2) selectively buffering the latched data as p2 words each having q2 bits, where p1q1=p2q2, and p2 and q2 are positive integers. The present invention also provides an electrical circuit for transforming a series of data having a first width into a series of data having a second width. A toggle buffer having a plurality of data latches selectively latches data having p1 words each having a q1 width, and buffers the latched data as p2 words each having q2 bits, where p1q1=p2q2, and p1, p2, q1, and q2 are positive integers. An input selector is coupled to the toggle buffer so as to provide a series of latching strobes to a first sequence of the latches. The input selector directs the data to be stored as p1 words, each word having q1 bits.
    Type: Grant
    Filed: February 12, 1991
    Date of Patent: July 16, 1996
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Eric J. Whitesell
  • Patent number: 5261263
    Abstract: An improved crimping tool mechanism with radially opposed jaws that direct and balance compressive forces toward the center of the work, joining cylindrical connectors and cables with more reliable electrical and mechanical contact than that obtainable using linear motion devices.
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: November 16, 1993
    Inventor: Eric J. Whitesell
  • Patent number: 4383432
    Abstract: A clock escapement monitoring device and method of accurately adjusting the escapement. The device comprises a sensor for monitoring the mechanical vibrations occurring at each excursion and producing an electrical pulse representative thereof; a standard clock of 100K Hertz; a signal conditioning circuit for conditioning the electrical excursion pulses and providing an audio output for monitoring audio signals representative of the mechanical vibrations; two frequency dividing trains, one for the conditioned excursion pulses and the other for the standard clock signal; and a display counter connected to the outputs of the frequency dividing trains wherein a visual display is produced representing the time of one excursion interval, the average time of ten excursion intervals, and the average time of one hundred excursion intervals; a regulated power supply; and a visual monitor for indicating a low power supply voltage.
    Type: Grant
    Filed: May 11, 1981
    Date of Patent: May 17, 1983
    Inventors: Nein T. Hoxsie, Eric J. Whitesell
  • Patent number: H1342
    Abstract: A method for the simultaneous bidirectional transfer of digital data at a ry high rate between a host digital data processor and an external device includes the steps of: loading the output data into a data register of the processor; loading an address reference of an external device into an address register of the processor; forming a composite address consisting of the sum of the data register and an address register; and exporting the output data through the address lines from the processor to the external device while simultaneously reading data into the processor from the external device. The method accomplishes rapid data transfer by advantageously transferring data over what would normally be address lines between the processor and the external device. This method is suitable for applications where data is to be transferred from a processor operably coupled to only one external device.
    Type: Grant
    Filed: December 7, 1990
    Date of Patent: August 2, 1994
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Eric J. Whitesell