Abstract: An apparatus for monitoring the status of the insulation on the wire in a winding in a device comprises a surrogate sample of insulating material having a thickness and properties selected to fail before the failure of the insulation on the wires in the winding, and a detector for detecting and indicating failure of the sample of insulating material. A method of monitoring the status of the insulation on the winding in a dynamoelectric device includes associating a surrogate sample of insulating material with the winding, monitoring the surrogate sample, and providing an alarm when the surrogate sample fails, which is predictive of the failure of the insulation on the winding wire.

Abstract: Power semiconductor device structures and assemblies with improved heat dissipation characteristics and low impedance interconnections include a thermally-conductive dielectric layer, such as diamondlike carbon (DLC) overlying at least portions of the active major surface of a semiconductor chip, with vias formed in the dielectric layer in alignment with contact pads on the active major surface. A patterned metallization layer is formed over the thermally-conductive dielectric layer, with portions of the metallization layer extending through the vias into electrical contact with the chip contact pads. A metal structure is electrically and thermally coupled to selected areas of the patterned metallization, such as by solder bonding or by a eutectic bonding process. In different embodiments, the metal structure may comprise a metal conductor bonded to the opposite major surface of another power semiconductor device structure, a heat-dissipating device-mounting structure, or simply a low-impedance lead.

Abstract: Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability.

Abstract: In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

Abstract: Substrate material is molded directly to semiconductor chips and other electrical components that are positioned for integrated circuit module fabrication. Chips having contact pads are placed face down on a layer of adhesive supported by a base. A mold form is positioned around the chips. Substrate molding material is added within the mold form, and the substrate molding material is then hardened. A dielectric layer having vias aligned with predetermined ones of the contact pads and having an electrical conductor extending through the vias is situated on the hardened substrate molding material and the faces of the chips. A thermal plug may be affixed to the backside of a chip before substrate molding material is added. A connector frame may be placed on the adhesive layer before substrate molding material is added. A dielectric layer may be placed over the backsides of the chips before the substrate molding material is added to enhance repairability.

Abstract: A high voltage P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface thereof. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup.+ cathode region, as viewed from above. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. In an exemplary embodiment, a MOSFET is included to alternately connect the further P.sup.+ region to the P.sup.- substrate and to open circuit the further P.sup.+ region. With the further P.sup. + region open circuited, the P-N diode has a low on-resistance when it operates in its current-conducting state.

Abstract: An integrated circuit in which a large potential can be maintained between the source of the device and the substrate on which this device and other devices are fabricated is described. The circuit employs a minority carrier sink region to remove minority carriers from the gate region of a MOS depletion device. The sink region is shielded from the substrate by a buried layer which prevents punch-through between the sink region and the substrate.

Abstract: A semiconductor wafer having a substrate with an epitaxial layer thereon includes a semiconductor device electrically isolated from the substrate as well as from any other devices in the wafer by electrical isolation structure comprising semiconductor material. The semiconductor device can accordingly be operated at high voltage with respect to the wafer substrate. The isolation structure in one form of the wafer comprises an N+ high voltage tub included in the wafer and a P+ ground region situated in the expitaxial layer, adjoining the substrate, and horizontally circumscribing the N+ high voltage tub and being spaced therefrom by a minimum layer extent of a portion of the epitaxial layer that is of N conductivity type.

Abstract: A power semiconductor device incorporates in its active, or current-carrying, region a main current section and an emulation current section. The active region is surrounded by a common device termination region. This is accomplished through provision of respective separate cathodes for the main and emulation current regions, while the device anode is common to both the main and emulation current sections. The current level in the emulation current section provides an accurate representation of the current level in the main current section since the main and emulation current sections are closely coupled both thermally and electrically and, further, are formed in the same fabrication process. The current level in the main current section can be economically determined with low power circuitry by way of sensing the current level in the emulation current section.

Abstract: An AC polyphase motor drive includes a current-controlled inverter comprising a plurality of semiconductor devices made up of power switches, such as IGBTs, and diodes. Current sensors integral with respective ones of a first group of the semiconductor devices sense the current delivered to each of the motor phase windings and a controller compares the sensed currents to a set of command signals to control operation of a second group of the semiconductor devices.

Abstract: High voltage semiconductor devices include a drift layer region underlying a field gate electrode, the drift layer region having a selected charge density of lesser magnitude than the charge density of the remainder of the drift layer. This tailoring of the charge density of the drift layer region lowers the pinch-off voltage of a MOSFET inherent in the drift layer region. This lower pinch-off voltage decreases the potential of a device buried-layer when the device is in a reverse blocking mode of operation.

Abstract: A P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. A P.sup.+ isolation region surrounds the periphery of the N.sup.- epitaxial layer and is integrally connected to the P.sup.- substrate. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface of such layer. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. The further P.sup.+ region is biased at the same potential as the P.sup.- substrate. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup. + cathode region. An N.sup.+ sinker region extends into the N.sup.