Abstract: A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Abstract: This method comprises the following steps: a) providing a stack successively comprising: a substrate; a first electrode; a first dielectric layer, having a first electrical strength; a second metal electrode; a second dielectric layer, having a second dielectric strength that is strictly less than the first dielectric strength; a third electrode; the first dielectric layer and the second electrode having a first interface, the second dielectric layer and the second electrode having a second interface; b) etching the stack by bombardment with electrically charged species, so as to define resistive memory cells; the bombardment of step b) being adapted so that electrically charged species accumulate at the first and second interfaces of each resistive memory cell, so as to generate an electric field that is strictly less than the first electrical strength and is strictly greater than the second dielectric strength.

Abstract: A filament type non-volatile memory device, includes a first electrode, a second electrode and an active layer extending between the first electrode and the second electrode, the active layer electrically interconnecting the first electrode to the second electrode, the device being suitable for having: a low resistive state, in which a conducting filament electrically interconnecting the first electrode to the second electrode uninterruptedly extends from end to end through the active layer, the filament having a low electric resistance, and a highly resistive state, in which the filament is broken, the filament having a high electric resistance. The device further includes a shunt resistance electrically connected in parallel to the active layer, between the first electrode and the second electrode.

Abstract: A memory device, containing a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, is produced. The oxide layer has a first zone and a second zone, with the first zone surrounding or being located on either side of the second zone, with the minimum distance d2 separating the two electrodes on the second zone of the oxide layer being less than the minimum distance d1 separating the two electrodes on the first zone of the oxide layer.

Abstract: The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical compounds, said method comprising the following steps: a step in which the electrically conductive substrate is placed in contact with chemical compounds comprising at least a disulfide terminal group; a step in which the disulfide terminal group of said chemical compounds is electro-oxidized, causing said chemical compounds to form a layer at the surface of the electrically conductive substrate.

Abstract: A memory device, containing a first electrode, a second electrode and an oxide layer arranged between the first electrode and the second electrode, is produced. The oxide layer has a first zone and a second zone, with the first zone surrounding or being located on either side of the second zone, with the minimum distance d2 separating the two electrodes on the second zone of the oxide layer being less than the minimum distance d1 separating the two electrodes on the first zone of the oxide layer.

Abstract: A process for obtaining an array of nanodots (212) for microelectronic devices, characterized in that it comprises the following steps: deposition of a silicon layer (210) on a substrate (100, 132), formation, above the silicon layer (210), of a layer (240) of a material capable of self-organizing, in which at least one polymer substantially forms cylinders (242) organized into an array within a matrix (244), formation of patterns (243) in the layer (240) of a material capable of self-organizing by elimination of the said cylinders (242), formation of a hard mask (312) by transfer of the said patterns (243), production of silicon dots (212) in the silicon layer (210) by engraving through the hard mask (312), silicidation of the silicon dots (212), comprising deposition of a metal layer (510).

Abstract: A method of making a non-volatile double-gate memory cell. The gate of the control transistor is formed with a relief of a semiconductor material on a substrate. The control gate of the memory transistor is formed with a sidewall of the relief of a semiconductor material configured to store electrical charge. A first layer is deposited so as to cover the stack of layers. The first layer is etched so as to form a first pattern juxtaposed on the relief. A second layer is formed on the first pattern. The second layer is etched so as to form on the first pattern a second pattern having a substantially plane upper face.

Abstract: The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical compounds, said method comprising the following steps: a step in which the electrically conductive substrate is placed in contact with chemical compounds comprising at least a disulfide terminal group; a step in which the disulfide terminal group of said chemical compounds is electro-oxidized, causing said chemical compounds to form a layer at the surface of the electrically conductive substrate.

Abstract: A process for manufacturing a stacked structure comprising at least one thin layer bonded to a target substrate, in which a thin layer is formed by introduction gaseous species into an initial substrate, to form a weakened layer separating a film from the rest of the initial substrate, a first contact face of the thin layer is bonded to a face of an intermediate substrate by molecular adhesion, and the initial substrate is fractured at the weakened layer so as to expose a free face of the thin layer. The intermediate substrate is then removed in order to obtain the stacked structure.

Abstract: The invention relates to a process for manufacturing a stacked structure comprising at least one thin layer bonding to a target substrate, comprising the following steps: a) formation of a thin layer starting from an initial substrate, the thin layer having a free face called the first contact face, b) putting the first contact face into bonding contact with a face of an intermediate support, the structure obtained being compatible with later thinning of the initial substrate, c) thinning of the said initial substrate to expose a free face of the thin layer called the second contact face and opposite the first contact face, d) putting a face of the target substrate into bonding contact with at least part of the second contact face, the structure obtained being compatible with later removal of all or some of the intermediate support, e) removal of at least part of the intermediate support in order to obtain the said stacked structure.

Abstract: A process for obtaining an array of nanodots (212) for microelectronic devices, characterized in that it comprises the following steps: deposition of a silicon layer (210) on a substrate (100, 132), formation, above the silicon layer (210), of a layer (240) of a material capable of self-organizing, in which at least one polymer substantially forms cylinders (242) organized into an array within a matrix (244), formation of patterns (243) in the layer (240) of a material capable of self-organizing by elimination of the said cylinders (242), formation of a hard mask (312) by transfer of the said patterns (243), production of silicon dots (212) in the silicon layer (210) by engraving through the hard mask (312), silicidation of the silicon dots (212), comprising deposition of a metal layer (510).

Abstract: An assembly method to enable local electrical bonds between zones located on a face of a first substrate and corresponding zones located on a face of a second substrate, the faces being located facing each other, at least one of the substrates having a surface topography. The method forms an intermediate layer including at least one burial layer on the face of the substrate or substrates having a surface topography to make it (them) compatible with molecular bonding of the faces of substrates to each other from a topographic point of view, resistivity and/or thickness of the intermediate layer being chosen to enable the local electrical bonds, brings the two faces into contact, the substrates positioned to create electrical bonds between areas on the first substrate and corresponding areas on the second substrate, and bonds the faces by molecular bonding.

Abstract: The invention relates to a DRAM memory device with a capacity associated with a field effect transistor, in which all or some of the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the capacity, or a flash-type memory using at least one field effect transistor, in which the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the floating grid of the transistor. The invention also relates to a method for producing on such device and to an electronic appliance comprising one such memory device.

Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.

Abstract: The invention relates to a compliant substrate (5) comprising a carrier (1) and at least one thin layer (4), formed on the surface of the carrier and intended to receive, in integral manner, a stress-giving structure. The carrier (1) and the thin layer (4) are joined to one another by joining means (3) such that the stresses brought by said structure are absorbed in whole or in part by the thin layer (4) and/or by the joining means (3) which comprise at least one joining zone chosen from among the following joining zones: a layer of microcavities and/or a bonding interface whose bonding energy is controlled to permit absorption of said stresses.

Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implanbumtation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.

Abstract: The invention relates to an assembly method to enable local electrical bonds between zones located on a face of a first substrate and corresponding zones located on a face of a second substrate, said faces being located facing each other, at least one of the substrates having a surface topography, characterised in that the method comprises steps consisting of: forming an intermediate layer comprising at least one burial layer on the face of the substrate or substrates having a surface topography to make it (them) compatible with molecular bonding of said faces of substrates to each other from a topographic point of view, the resistivity and/or thickness of the intermediate layer being chosen to enable said local electrical bonds, bringing the two faces into contact, the substrates being positioned so as to create electrical bonds between areas located on the first substrate and the corresponding areas located on the second substrate, bonding the faces of the first and second substrates by molecular bonding

Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implantation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.

Abstract: The invention relates to a DRAM memory device with a capacity associated with a field effect transistor, in which all or some of the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the capacity, or a flash-type memory using at least one field effect transistor, in which the molecules capable of storing the loads comprising a polyoxometallate are incorporated into the floating grid of the transistor.