Patents by Inventor Eric M. Shiflet

Eric M. Shiflet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11892182
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 6, 2024
    Assignee: Uplight, Inc.
    Inventor: Eric M. Shiflet
  • Publication number: 20220035329
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Application
    Filed: June 11, 2021
    Publication date: February 3, 2022
    Inventor: Eric M. Shiflet
  • Patent number: 11042141
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: June 22, 2021
    Assignee: Uplight, Inc.
    Inventor: Eric M. Shiflet
  • Publication number: 20190361417
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Application
    Filed: August 12, 2019
    Publication date: November 28, 2019
    Inventor: Eric M. Shiflet
  • Patent number: 10379508
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: August 13, 2019
    Assignee: Tendril Networks, Inc.
    Inventor: Eric M. Shiflet
  • Publication number: 20160298868
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Application
    Filed: March 25, 2016
    Publication date: October 13, 2016
    Inventor: Eric M. Shiflet
  • Patent number: 9310815
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 12, 2016
    Assignee: Tendril Networks, Inc.
    Inventor: Eric M. Shiflet
  • Publication number: 20140229016
    Abstract: A facility for performing setpoint adjustment-based duty cycling techniques by adjusting the setpoint of a device or component is described. The facility reduces energy consumption for a system, such as an HVAC system, or device by adjusting or modulating an associated setpoint or temperature setting. The facility modulates the setpoint between a base setpoint value and another setpoint value based on a mode of the system. When the system is in a cooling mode, the facility modulates the temperature between the base setpoint value and a higher setpoint value. When the system is in heating mode, the facility modulates the temperature between the base setpoint value and a lower setpoint value. The facility may modulate the setpoint between the two setpoint values based on an offset value or a fixed setpoint value.
    Type: Application
    Filed: February 12, 2013
    Publication date: August 14, 2014
    Applicant: TENDRIL NETWORKS, INC.
    Inventor: Eric M. Shiflet
  • Publication number: 20120068854
    Abstract: The present invention can provide a method, apparatus, and system for providing energy usage information to a user. One embodiment displays, on a display interface of a display device, a virtual analog clock and receives energy usage data for a metered environment. A graphical representation of a first level of the energy usage data is displayed on the face of the virtual analog clock, with the graphical representation including at least one display element.
    Type: Application
    Filed: March 21, 2011
    Publication date: March 22, 2012
    Inventors: Eric M. Shiflet, Dennis Kyle, Scott S. Ballantyne, Gowrishankar Bharadwaj
  • Patent number: 7949974
    Abstract: A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: May 24, 2011
    Assignee: Xilinx, Inc.
    Inventors: Jason J. Moore, Ian L. McEwen, Reto Stamm, John Damian Corbett, Eric M. Shiflet
  • Patent number: 7640527
    Abstract: Method, apparatus, and computer readable medium for circuit design for a programmable device is described. In one example, a logical description of a circuit design having static logic and reconfigurable logic is imported into a graphical environment. The circuit design is processed in the graphical environment. In particular, the logical description is floorplanned to locate the static logic and the reconfigurable logic in a floorplan of the programmable device. At least one design rule check (DRC) is performed. A partial reconfiguration implementation of the circuit design is then managed for the programmable device.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 29, 2009
    Assignee: XILINX, Inc.
    Inventors: Nij Dorairaj, Eric M. Shiflet
  • Patent number: 7620927
    Abstract: A method of implementing a circuit design can include selecting the circuit design to be implemented, wherein the circuit design comprises a plurality of partitions, and receiving a user input specifying a value of a partition property. The partition property can be associated with a selected one of the plurality of partitions of the circuit design. The method also can include performing an incremental implementation flow upon the circuit design for implementation by, at least in part, selectively modifying portions of a prior implementation of the selected partition in accordance with the value of the partition property.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: November 17, 2009
    Assignee: XILINX, Inc.
    Inventors: Emil S. Ochotta, William W. Stiehl, Eric M. Shiflet, W. Story Leavesley, III
  • Patent number: 6423572
    Abstract: The present invention relates to integrated circuit packaging useful for programmable logic devices. The invention provides a migration path between a base integrated circuit and an extended integrated circuit that is a functional superset of the base. In the case of a programmable logic device (PLD), the pin element layout for a base integrated circuit provides for the connection of power, control, and I/O signals. Pins conducting power signals are located at the core of the base pin layout. Pins conducting control signals are located near the intersections of the horizontal and vertical axes of the layout and the perimeter of the layout. Remaining pins conduct I/O signals. The pin element layout for an extended integrated circuit subsumes the base pin element layout. Additional pins for conducting power signals are located near one or more diagonal axes of the extended pin element layout.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: July 23, 2002
    Assignee: Altera Corporation
    Inventor: Eric M. Shiflet
  • Patent number: 6417692
    Abstract: A programmable input/output cell (I/O cell) for use with integrated circuits, and in particular programmable logic devices, is presented comprising input receiver circuitry, output driver circuitry and programmable elements. The input receiver and output driver circuitry each include multiple receivers/drivers that provide an interface between the signaling level of the integrated circuit and at least two other signaling standards. The programmable elements may be programmed to select a different signaling standard for each I/O cell to operate at, if desired. For instance, adjacent I/O cells may be connected to two different bus structures that utilize different signaling levels. The invention enables one I/O cell to translate between the PLD signaling level and the first bus signaling level, while the second I/O cell translates between the integrated circuit signaling level and the second bus signaling level.
    Type: Grant
    Filed: February 5, 2001
    Date of Patent: July 9, 2002
    Assignee: Altera Corporation
    Inventor: Eric M. Shiflet
  • Publication number: 20020022356
    Abstract: The present invention relates to integrated circuit packaging useful for programmable logic devices. The invention provides a migration path between a base integrated circuit and an extended integrated circuit that is a functional superset of the base. In the case of a programmable logic device (PLD), the pin element layout for a base integrated circuit provides for the connection of power, control, and I/O signals. Pins conducting power signals are located at the core of the base pin layout. Pins conducting control signals are located near the intersections of the horizontal and vertical axes of the layout and the perimeter of the layout. Remaining pins conduct I/O signals. The pin element layout for an extended integrated circuit subsumes the base pin element layout. Additional pins for conducting power signals are located near one or more diagonal axes of the extended pin element layout.
    Type: Application
    Filed: August 8, 2001
    Publication date: February 21, 2002
    Inventor: Eric M. Shiflet
  • Patent number: 6297565
    Abstract: The present invention relates to integrated circuit packaging useful for programmable logic devices. The invention provides a migration path between a base integrated circuit and an extended integrated circuit that is a functional superset of the base. In the case of a programmable logic device (PLD), the pin element layout for a base integrated circuit provides for the connection of power, control, and I/O signals. Pins conducting power signals are located at the core of the base pin layout. Pins conducting control signals are located near the intersections of the horizontal and vertical axes of the layout and the perimeter of the layout. Remaining pins conduct I/O signals. The pin element layout for an extended integrated circuit subsumes the base pin element layout. Additional pins for conducting power signals are located near one or more diagonal axes of the extended pin element layout.
    Type: Grant
    Filed: March 30, 1999
    Date of Patent: October 2, 2001
    Assignee: Altera Corporation
    Inventor: Eric M. Shiflet
  • Publication number: 20010009379
    Abstract: A programmable input/output cell (I/O cell) for use with integrated circuits, and in particular programmable logic devices, is presented comprising input receiver circuitry, output driver circuitry and programmable elements. The input receiver and output driver circuitry each include multiple receivers/drivers that provide an interface between the signaling level of the integrated circuit and at least two other signaling standards. The programmable elements may be programmed to select a different signaling standard for each I/O cell to operate at, if desired. For instance, adjacent I/O cells may be connected to two different bus structures that utilize different signaling levels. The invention enables one I/O cell to translate between the PLD signaling level and the first bus signaling level, while the second I/O cell translates between the integrated circuit signaling level and the second bus signaling level.
    Type: Application
    Filed: February 5, 2001
    Publication date: July 26, 2001
    Applicant: Altera Corporation
    Inventor: Eric M. Shiflet
  • Patent number: 6239612
    Abstract: A programmable input/output cell (I/O cell) for use with integrated circuits, and in particular programmable logic devices, is presented comprising input receiver circuitry, output driver circuitry and programmable elements. The input receiver and output driver circuitry each include multiple receivers/drivers that provide an interface between the signaling level of the integrated circuit and at least two other signaling standards. The programmable elements may be programmed to select a different signaling standard for each I/O cell to operate at, if desired. For instance, adjacent I/O cells may be connected to two different bus structures that utilize different signaling levels. The invention enables one I/O cell to translate between the PLD signaling level and the first bus signaling level, while the second I/O cell translates between the integrated circuit signaling level and the second bus signaling level.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: May 29, 2001
    Assignee: Altera Corporation
    Inventor: Eric M. Shiflet