Abstract: A TDM data distribution system (10) includes a hub unit (12) with a multipoint transmitter (24) and any number of subscriber units (14), each of which has a multipoint receiver (28). A forward communication link (16) transmitted by the hub unit (12) exhibits a substantially constant baud and carrier frequency over a number of diverse modulation format (MF) time slots (42). However, the different MF slots (42) convey data using different modulation formats. Modulation order and coding rate may vary for different modulation formats. The multipoint transmitter (24) includes a number of encoding FEC processors (48), wherein each encoding FEC processor (48) is active only for selected ones of the different MF slots (42). When inactive, the internal states of the encoding FEC processors (48) are frozen. Each multipoint receiver (28) includes a decoding FEC processor (108) which is active only for MF slots (42) assigned to the same modulation format for which the decoding FEC processors (108) are programmed.

Abstract: An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).

Abstract: An IC modulation processor (28) may be configured to operate in a single chip mode to accommodate baud rates up to a maximum clock rate for the processor (28) and in a dual chip mode to accommodate baud rates in excess of the maximum clock rate. The IC modulation processor (28) performs digital processing on a communication signal which conveys an input data stream (22). A pulse shaping filter (54-57) is provided following a phase mapper (50). The pulse shaping filter (54-57) is implemented as a pair of half-filters. Pulse shaping is distributed between two IC modulation processors (28) in the dual chip mode. An interpolator (86) and linearizer (106) follow the pulse shaping filters (54-57).

Abstract: A digital data receiver includes a tunable analog matched filter circuit having a variable bandwidth responsive to the bit error rate (BER) of the decoded data. The bandwidth of the analog filtering circuit is controlled by a tuning control signal that includes a coarse tuning signal combined with a fine tuning signal. The coarse tuning signal is generated by a frequency-to-current converter and the fine tuning signal is generated by a current-scaling digital-to-analog converter (DAC). The DAC input signal is produced by a DAC control circuit that includes a BER comparator and a DAC control state machine. The BER comparator determines whether the BER has improved or degraded in response to a previous tuning command. To optimize the BER in the decoded data signal, the state machine increments or decrements the value of the fine tuning signal, which in turn alters the filter bandwidth.

Abstract: A pulse width modulation (PWM) circuit translates digital data into an analog signal. The PWM circuit includes at least a digital counter, a significance reverser, and a comparator circuit. The significance reverser reverses the relative order of significance of at least two bits in the count words generated by the counter. The comparator determines whether the magnitude of a digital input word is greater than the magnitude of the reversed order count word. The PWM circuit produces a high output when the magnitude of the input word is greater than the magnitude of the reversed order count word and a low output when the magnitude of the input word is not greater than the magnitude of the reversed order count word. The analog output produced by the PWM circuit includes a number of pulses evenly distributed during the count cycle of the counter, and the input word indicates a duty cycle for the analog output.

Abstract: A digital data receiver includes tunable analog components having variable parameters that are responsive to the bit error rate (BER) of the decoded digital data. The analog components include a quadrature generator having a tunable phase shifter, an analog filter having a tunable bandwidth, a tunable magnitude equalizer circuit, a tunable group delay equalizer circuit, and an amplifier having an adjustable gain. The tunable components are controlled by tuning control signals that incorporate digitally-produced fine tuning signals. The digital tuning signals are altered in accordance with realtime changes in the BER.