Abstract: Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.

Abstract: Method and system for chip optimization using model based verification (MBV) tool provide more accurate verification in determining hotspots and their characteristics. The MBV and the layout optimizer are implemented within a feedback loop. This type of verification allows for the MBV tool to provide hints, constraints and hotspot information to the layout optimizer. In addition, the model-based simulation results can be used to automatically fix the circuit designs and allow for specialized optimization flow for standard cell libraries.

Abstract: Disclosed is a method, system, and computer program product for performing edge optimization on an electronic design. According to some approaches, the number of edges and/or the length of edges within an IC design are configured for optimized manufacturability and yield of an integrated circuit. The edge optimization may occur in real-time during layout, placement, and/or routing, or occur in a post-optimization step.

Abstract: Disclosed is a method, system, and computer program product for implementing model-based layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that the layout can be formed with a high degree of manufacturability from the outset.

Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Abstract: Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.

Abstract: Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.

Abstract: Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are considered as a collective object or shape, based upon the proximity of one or more of the objects to one or more other objects. The type and/or configuration of the collective object is based, for example, upon the type of rule that is being considered for the layout, placement, or routing operation.

Abstract: An improved method, system, user interface, and computer program product is described for using a memory and learning component to improve capacitance and resistance estimates based on the types of layouts and devices being evaluated. According to some approaches, a learning component is implemented that uses recommended test sets from the evaluation component to automatically test the extraction estimates against the field solver. Variability models from manufacturing or electrical analysis may also be used to select a series of objects (unique conductor geometries) that make up a conduction path or net or specific conductor geometries for evaluation and additional learning improvement.

Abstract: Disclosed is an improved method and system for implementing parallelism for execution of electronic design automation (EDA) tools, such as layout processing tools. Examples of EDA layout processing tools are placement and routing tools. Efficient locking mechanism are described for facilitating parallel processing and to minimize blocking.

Abstract: A method and mechanism is disclosed for identifying spacing and clearance based rule violations in an IC design. Shadows are employed to identify spacing and clearance based rule violations. The shadow approach of is particularly useful to identify width-dependent spacing and clearance violations, while avoiding false positives that exist with alternate approaches. The embodiments can be used with any type, configuration, or shape of layout objects.

Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Abstract: A method and mechanism is disclosed for identifying connected shapes and objects in an electrical design. The entire hierarchical design does not have to be flattened to perform the operation of identifying connected objects for a specific object. Instead of unfolding the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes need to be unfolded to perform the search.

Abstract: Disclosed is a method, system, and computer program product for implementing model-based layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout. In effect, the parameters that are used for placement and routing are guided by the model data so that the layout can be formed with a high degree of manufacturability from the outset.

Abstract: Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations.

Abstract: A method of analyzing a design of an electronic circuit uses slices. The method includes generating one or more slices, each slice comprising a contiguous region of the design, and generating an set comprising one or more bins for each slice. A search for an object may be performed by determining a search area, and identifying slices containing at least a portion of the search area. For each identified slice, each object within the search area is associated with one of the bins of the set for the slice.

Abstract: A method of analyzing a design of an electronic circuit includes tessellating the design into a grid of rectangles, selecting at least one rectangle as a first level parent rectangle, and generating a plurality of second level child rectangles based on the first level parent rectangle.

Abstract: A method of simulating a design of an electronic system having multiple layers includes, for each layer, storing a plurality of shape occurrences for the layer. A hierarchy of shape instances having a plurality of levels is generated. Each shape instance corresponds to one of the shape occurrences. A hierarchy of shadow instances having a plurality of levels is generated.

Abstract: A method of analyzing a design of an electronic circuit may include selecting a query object in a collection of sets of intervals for the design, where each set of intervals along a first common axis, the collection of sets along a second common axis. Candidate objects within the collection that are candidates to be closest to the query object may be identified. A nearest neighbor object is selected from the candidate objects, the nearest neighbor object having shortest distance to the query object.